K
Kumar Yelamarthi
Guest
Hi All,
I had designed an high speed adder design at the transistor level
using Cadence Virtuoso. I am looking for tools that take the
transistor level netlist or schematic and generate a clock tree
automatically for the design. When I tried looking for the same in the
forums, some one in one of the forum said a few years ago that it can
be done using Gate Ensemble. But when I checked the Cadence website, I
was not able to find any information on it at all. Can anyone please
suggest me tools that generate a clock tree by taking the transistor
level netlist or schematic?
Thank you for your help in advance.
Kumar
I had designed an high speed adder design at the transistor level
using Cadence Virtuoso. I am looking for tools that take the
transistor level netlist or schematic and generate a clock tree
automatically for the design. When I tried looking for the same in the
forums, some one in one of the forum said a few years ago that it can
be done using Gate Ensemble. But when I checked the Cadence website, I
was not able to find any information on it at all. Can anyone please
suggest me tools that generate a clock tree by taking the transistor
level netlist or schematic?
Thank you for your help in advance.
Kumar