Guest
Hi all,
I am currently implementing a module which has large number of
registers(the datapath is heavily pipelined and lotsa registers). To
reduce the area of the design , I have replaced many of the internal
registers ,with FFs without a RESET pin.
So now all the internal register dont get cleared (reset) while
applying an external reset. they just keep on shifting unknown value,
until the actual data fills in the pipeline. this is perfectly
acceptable for me except for the initial X's I see in waveform, till
the actual data reaches to the point.
I save around 10-15% area by this way. (in a total size of ~90K).
My module is part of a ~1.5Mgates asic.
I want to ask you people , whether this method of reducing area will
cause any problems(in the design flow) considering the total system.
please giveme ur valuable suggestions.
thanks a lot
Deepu John
I am currently implementing a module which has large number of
registers(the datapath is heavily pipelined and lotsa registers). To
reduce the area of the design , I have replaced many of the internal
registers ,with FFs without a RESET pin.
So now all the internal register dont get cleared (reset) while
applying an external reset. they just keep on shifting unknown value,
until the actual data fills in the pipeline. this is perfectly
acceptable for me except for the initial X's I see in waveform, till
the actual data reaches to the point.
I save around 10-15% area by this way. (in a total size of ~90K).
My module is part of a ~1.5Mgates asic.
I want to ask you people , whether this method of reducing area will
cause any problems(in the design flow) considering the total system.
please giveme ur valuable suggestions.
thanks a lot
Deepu John