Need some Verilog help...

[Ted Larson]

I am trying to learn Verilog. I got myself a couple of books on it, and I
have written a few small, designs that work. Anyway, now I am trying to do
something more useful, and I am getting stuck. I have been using the Xilinx
WebPack ISE 6.2 for synthesis, and it constantly is giving me all kinds of
warnings.

What I am trying to do is a counter, where I can set it to a shift register,
and then shift the bits of the current count out serially using a clock.
Here is what I have:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge reset)
begin
if(reset)
count<=8'b00000000;
else
tbuf <= {tbuf[6:0], 1'b0};
end

always @(posedge flick)
begin
count<=count+1;
end

always @(posedge set)
tbuf <= count;

assign sout = tbuf[7];

endmodule


Seems simple enough....although I get warnings like the following, and I
can't synthesize it:

WARNING:Xst:1426 - The value init of the FF/Latch count_0 hinder the
constant cleaning in the block sercount4.
You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch <count_5> (without init value) is constant in
block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_7>
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_6>
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_1>
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_2>
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_3>
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_4>
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tbuf_0>
(without init value) is constant in block <sercount4>.
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_7> not
replaced by logic
Sources are: tbuf_ren_7:Q, tbuf_7:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <count_0> not
replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_2> not
replaced by logic
Sources are: tbuf_ren_2:Q, tbuf_2:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_ren_0>
not replaced by logic
Sources are: count<5>:count<5>, count<7>:count<7>, count<6>:count<6>,
count<1>:count<1>, count<2>:count<2>, count<3>:count<3>, count<4>:count<4>,
tbuf_ren_0:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_1> not
replaced by logic
Sources are: tbuf_ren_1:Q, tbuf_1:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_3> not
replaced by logic
Sources are: tbuf_ren_3:Q, tbuf_3:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_6> not
replaced by logic
Sources are: tbuf_ren_6:Q, tbuf_6:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_5> not
replaced by logic
Sources are: tbuf_ren_5:Q, tbuf_5:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_4> not
replaced by logic
Sources are: tbuf_ren_4:Q, tbuf_4:Q
ERROR:Xst:415 - Synthesis failed

Can someone make some suggestions on what I am doing wrong?

Thanks,

- Ted
ted@larsonland.com

 

[Jason Zheng]

Ted Larson wrote:

I am trying to learn Verilog. I got myself a couple of books on it, and I
have written a few small, designs that work. Anyway, now I am trying to do
something more useful, and I am getting stuck. I have been using the Xilinx
WebPack ISE 6.2 for synthesis, and it constantly is giving me all kinds of
warnings.

What I am trying to do is a counter, where I can set it to a shift register,
and then shift the bits of the current count out serially using a clock.
Here is what I have:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge reset)
begin
if(reset)
count<=8'b00000000;
else
tbuf <= {tbuf[6:0], 1'b0};
end

always @(posedge flick)
begin
count<=count+1;
end

always @(posedge set)
tbuf <= count;

assign sout = tbuf[7];

endmodule

First, you shouldn't have had multiple always assignments to one reg
type, that's a big no-no. Put all the assignments to tbuf in one always
statement like this:

always @ (posedge clk)
if (set) tbuf <= count;
else tbuf <= {tbuf[6:0], 1'b0};

or, to make set an asynchoronous signal,

always @ (posedge clk or posedge set)
if (set) tbuf <= count;
else tbuf <= {tbuf[6:0], 1'b0};

But I recommend the former since it's not a time-critical reset.

Secondly, your count operates on two different clocks: clk and flick.
That will confuse the synthesizer. You should only use one clock for a
flop. I don't understand why you have to use two clock here.

always @ (posedge clk or posedge reset)
if (reset) count <= 8'h00;
else count <= count + 1;

 

[Blackie Beard]

Possibly your coding style is confusing the synthesis tool.
It is more correct to keep the functions related to one register
within one "always" block.

Additionally, for later portability, you should design with
just one clock, so all your circuits are singing to the same
hymnal. But you are using flick as another clock by
referencing to it's edge. Instead, use flick as a condition.


always @(posedge clk or posedge reset)
if(reset) count<=8'h00;
else if (flick) count <= count + 8'h01;

always @(posedge clk or posedge reset)
if(reset) tbuf[7:0] <= 0; // initialize!
else tbuf <= {tbuf[6:0], 1'b0};

assign sout = tbuf[7];

by the way I don't know what is shifted in tbuf[7], or if
it is even getting initialized. I'm not sure what function
you intend for tbuf[7:0], either. Probably you need to
give that some further thought.

BB


===================================================

"Ted Larson" <ted@corticalsoftware.com> wrote in message
news:ce3cv0$9l2@dispatch.concentric.net...

I am trying to learn Verilog. I got myself a couple of books on it, and I
have written a few small, designs that work. Anyway, now I am trying to
do
something more useful, and I am getting stuck. I have been using the
Xilinx
WebPack ISE 6.2 for synthesis, and it constantly is giving me all kinds of
warnings.

What I am trying to do is a counter, where I can set it to a shift
register,
and then shift the bits of the current count out serially using a clock.
Here is what I have:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge reset)
begin
if(reset)
count<=8'b00000000;
else
tbuf <= {tbuf[6:0], 1'b0};
end

always @(posedge flick)
begin
count<=count+1;
end

always @(posedge set)
tbuf <= count;

assign sout = tbuf[7];

endmodule


Seems simple enough....although I get warnings like the following, and I
can't synthesize it:

WARNING:Xst:1426 - The value init of the FF/Latch count_0 hinder the
constant cleaning in the block sercount4.
You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch <count_5> (without init value) is constant in
block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_7
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_6
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_1
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_2
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_3
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_4
(without init value) is constant in block <sercount4>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tbuf_0
(without init value) is constant in block <sercount4>.
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_7> not
replaced by logic
Sources are: tbuf_ren_7:Q, tbuf_7:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <count_0> not
replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_2> not
replaced by logic
Sources are: tbuf_ren_2:Q, tbuf_2:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_ren_0
not replaced by logic
Sources are: count<5>:count<5>, count<7>:count<7>, count<6>:count<6>,
count<1>:count<1>, count<2>:count<2>, count<3>:count<3>,
count<4>:count<4>,
tbuf_ren_0:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_1> not
replaced by logic
Sources are: tbuf_ren_1:Q, tbuf_1:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_3> not
replaced by logic
Sources are: tbuf_ren_3:Q, tbuf_3:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_6> not
replaced by logic
Sources are: tbuf_ren_6:Q, tbuf_6:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_5> not
replaced by logic
Sources are: tbuf_ren_5:Q, tbuf_5:Q
WARNING:Xst:528 - Multi-source in Unit <sercount4> on signal <tbuf_4> not
replaced by logic
Sources are: tbuf_ren_4:Q, tbuf_4:Q
ERROR:Xst:415 - Synthesis failed

Can someone make some suggestions on what I am doing wrong?

Thanks,

- Ted
ted@larsonland.com

 

[Ted Larson]

Excellent suggestions! This is exactly what I needed....whew. I thought I
was going to drive myself crazy trying to figure that one out. I will
definitely try to keep all the LHS work of registers within the same always
block from now on. That was the problem for sure. I attached a
synthesizable version below so you can see the changes I made based upon
your suggestions. Yay! No more warnings or errors!

Additionally, for later portability, you should design with
just one clock, so all your circuits are singing to the same
hymnal. But you are using flick as another clock by
referencing to it's edge. Instead, use flick as a condition.

HOWEVER, this question brings up a larger question on my whole design. I
had two clocks in there because what I am trying to do, is build a pulse
counter, that stores a total number of pulses, and then I can retrieve them
using an externally clocked serial connection (SPI like). One clock is the
pulses I want to count. The other clock is used for clocking the serial
data out at my leisure.

Given the problem I am trying to solve...and obviously for general types of
scenarios like this one.....do you think it is a better overall practice, to
just have one master clock that is considerably faster than all the clocking
conditions I have, and then just poll the two other clock lines? Or do you
think it is better to have everything edge-triggered like I have done below?

Thanks again for all your help. Very good info.

- Ted
ted@larsonland.com

This one will synthesize now:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge set)
begin
if(set)
tbuf <= count;
else
tbuf <= tbuf << 1;
end

always @(posedge flick or posedge reset)
begin
if(reset)
count <= 8'h00;
else
count <= count+1;
end

assign sout = tbuf[7];

endmodule

 

[Blackie Beard]

"Ted Larson" <ted@corticalsoftware.com> wrote in message
news:ce3jhl$f0h@dispatch.concentric.net...

Excellent suggestions! This is exactly what I needed....whew. I thought
I
was going to drive myself crazy trying to figure that one out. I will
definitely try to keep all the LHS work of registers within the same
always
block from now on. That was the problem for sure. I attached a
synthesizable version below so you can see the changes I made based upon
your suggestions. Yay! No more warnings or errors!

What's funny is that a lot of simulators will let you get away with stuff
like that. Simulators only look for certain types of errors. But
synthesis tools will let you get away with other types of errors, as
long as it thinks there's a chance they could be intentional.

Additionally, for later portability, you should design with
just one clock, so all your circuits are singing to the same
hymnal. But you are using flick as another clock by
referencing to it's edge. Instead, use flick as a condition.


HOWEVER, this question brings up a larger question on my whole design. I
had two clocks in there because what I am trying to do, is build a pulse
counter, that stores a total number of pulses, and then I can retrieve
them
using an externally clocked serial connection (SPI like). One clock is
the
pulses I want to count. The other clock is used for clocking the serial
data out at my leisure.

Given the problem I am trying to solve...and obviously for general types
of
scenarios like this one.....do you think it is a better overall practice,
to
just have one master clock that is considerably faster than all the
clocking
conditions I have, and then just poll the two other clock lines? Or do
you
think it is better to have everything edge-triggered like I have done
below?

I'm assuming your pulse count is going to be much lower than your free-
running counter (which you are using to time the periodic communication).
No - you can certainly use the same clock for both.

Now you have to count, for example, posedge of incoming, and you are
using a different posedge for system clk. run the posedge of incoming
into the set of an RSFF, and run the RSFF's reset to it's output anded
with system clock == 1. (If the incoming pulsewidths are guaranteed by
design to be less than your system clock, this should work well). I myself
hate using primatives and megafunctions, or whatever. I like to use fully
behavior code, so for that one I would make the RSFF out of combinatorial
loop logic (as long as you provide reset it's cool). I have one working but
I've got to run to work - get back later.

BB

Thanks again for all your help. Very good info.

- Ted
ted@larsonland.com

This one will synthesize now:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge set)
begin
if(set)
tbuf <= count;
else
tbuf <= tbuf << 1;
end

always @(posedge flick or posedge reset)
begin
if(reset)
count <= 8'h00;
else
count <= count+1;
end

assign sout = tbuf[7];

endmodule

 

[Blackie Beard]

"Blackie Beard" <bb@fearlessimmortalwretch.com> wrote in message
news:ZrtOc.3057$8k.1843@fed1read03...

"Ted Larson" <ted@corticalsoftware.com> wrote in message
news:ce3jhl$f0h@dispatch.concentric.net...
Excellent suggestions! This is exactly what I needed....whew. I
thought
I
was going to drive myself crazy trying to figure that one out. I will
definitely try to keep all the LHS work of registers within the same
always
block from now on. That was the problem for sure. I attached a
synthesizable version below so you can see the changes I made based upon
your suggestions. Yay! No more warnings or errors!

What's funny is that a lot of simulators will let you get away with stuff
like that. Simulators only look for certain types of errors. But
synthesis tools will let you get away with other types of errors, as
long as it thinks there's a chance they could be intentional.



Additionally, for later portability, you should design with
just one clock, so all your circuits are singing to the same
hymnal. But you are using flick as another clock by
referencing to it's edge. Instead, use flick as a condition.


HOWEVER, this question brings up a larger question on my whole design.
I
had two clocks in there because what I am trying to do, is build a pulse
counter, that stores a total number of pulses, and then I can retrieve
them
using an externally clocked serial connection (SPI like). One clock is
the
pulses I want to count. The other clock is used for clocking the serial
data out at my leisure.

Given the problem I am trying to solve...and obviously for general types
of
scenarios like this one.....do you think it is a better overall
practice,
to
just have one master clock that is considerably faster than all the
clocking
conditions I have, and then just poll the two other clock lines? Or do
you
think it is better to have everything edge-triggered like I have done
below?


I'm assuming your pulse count is going to be much lower than your free-
running counter (which you are using to time the periodic communication).
No - you can certainly use the same clock for both.

Now you have to count, for example, posedge of incoming, and you are
using a different posedge for system clk. run the posedge of incoming
into the set of an RSFF, and run the RSFF's reset to it's output anded
with system clock == 1. (If the incoming pulsewidths are guaranteed by
design to be less than your system clock, this should work well). I
myself
hate using primatives and megafunctions, or whatever. I like to use fully
behavior code, so for that one I would make the RSFF out of combinatorial
loop logic (as long as you provide reset it's cool). I have one working
but
I've got to run to work - get back later.

BB

Yeah, you need like this:

wire ain1, aout1;
assign #1 aout1 = ain1 | (hold & aout1);
// (the "#1" is needed for simulation).
assign ain1 = pulse_input; // that you are trying to measure
assign hold = ~clk; // clk will clear the flop after you've got edge
captured

....
else if (aout1) counter <= counter + ?'h1; // increment positive edge
count

Thanks again for all your help. Very good info.

- Ted
ted@larsonland.com

This one will synthesize now:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge set)
begin
if(set)
tbuf <= count;
else
tbuf <= tbuf << 1;
end

always @(posedge flick or posedge reset)
begin
if(reset)
count <= 8'h00;
else
count <= count+1;
end

assign sout = tbuf[7];

endmodule

 

[Blackie Beard]

"Blackie Beard" <bb@fearlessimmortalwretch.com> wrote in message
news:EXQOc.6545$8k.1083@fed1read03...

"Blackie Beard" <bb@fearlessimmortalwretch.com> wrote in message
news:ZrtOc.3057$8k.1843@fed1read03...

"Ted Larson" <ted@corticalsoftware.com> wrote in message
news:ce3jhl$f0h@dispatch.concentric.net...
Excellent suggestions! This is exactly what I needed....whew. I
thought
I
was going to drive myself crazy trying to figure that one out. I will
definitely try to keep all the LHS work of registers within the same
always
block from now on. That was the problem for sure. I attached a
synthesizable version below so you can see the changes I made based
upon
your suggestions. Yay! No more warnings or errors!

What's funny is that a lot of simulators will let you get away with
stuff
like that. Simulators only look for certain types of errors. But
synthesis tools will let you get away with other types of errors, as
long as it thinks there's a chance they could be intentional.



Additionally, for later portability, you should design with
just one clock, so all your circuits are singing to the same
hymnal. But you are using flick as another clock by
referencing to it's edge. Instead, use flick as a condition.


HOWEVER, this question brings up a larger question on my whole design.
I
had two clocks in there because what I am trying to do, is build a
pulse
counter, that stores a total number of pulses, and then I can retrieve
them
using an externally clocked serial connection (SPI like). One clock
is
the
pulses I want to count. The other clock is used for clocking the
serial
data out at my leisure.

Given the problem I am trying to solve...and obviously for general
types
of
scenarios like this one.....do you think it is a better overall
practice,
to
just have one master clock that is considerably faster than all the
clocking
conditions I have, and then just poll the two other clock lines? Or
do
you
think it is better to have everything edge-triggered like I have done
below?


I'm assuming your pulse count is going to be much lower than your free-
running counter (which you are using to time the periodic
communication).
No - you can certainly use the same clock for both.

Now you have to count, for example, posedge of incoming, and you are
using a different posedge for system clk. run the posedge of incoming
into the set of an RSFF, and run the RSFF's reset to it's output anded
with system clock == 1. (If the incoming pulsewidths are guaranteed by
design to be less than your system clock, this should work well). I
myself
hate using primatives and megafunctions, or whatever. I like to use
fully
behavior code, so for that one I would make the RSFF out of
combinatorial
loop logic (as long as you provide reset it's cool). I have one working
but
I've got to run to work - get back later.

BB


Yeah, you need like this:

wire ain1, aout1;
assign #1 aout1 = ain1 | (hold & aout1);
// (the "#1" is needed for simulation).
assign ain1 = pulse_input; // that you are trying to measure
assign hold = ~clk; // clk will clear the flop after you've got edge
captured

...
else if (aout1) counter <= counter + ?'h1; // increment positive edge
count

Come to think of it - this may not work because the flop after clearing
will continue to acquire because your pulse is still high.

You don't need then an RSFF. You just need to capture the edge,
right?

reg r1, r2;

always @(posedge clk)
begin
r1 <= pulse_in;
r2 <= r1;
end

assign increment_counter = (r1 == 1 & r2 == 0);

That should work.

Thanks again for all your help. Very good info.

- Ted
ted@larsonland.com

This one will synthesize now:

module sercount4(clk,flick,set,reset,sout);
input clk;
input flick;
input set;
input reset;
output sout;

reg [7:0] count;
reg [7:0] tbuf;

always @(posedge clk or posedge set)
begin
if(set)
tbuf <= count;
else
tbuf <= tbuf << 1;
end

always @(posedge flick or posedge reset)
begin
if(reset)
count <= 8'h00;
else
count <= count+1;
end

assign sout = tbuf[7];

endmodule