Need some help!

Why am I getting this error:

ERROR:Xst:528 - Multi-source in Unit <waittime> on signal <z>
Sources are:
Signal <z> in Unit <waittime> is assigned to GND
ERROR:Xst:415 - Synthesis failed
CPU : 1.72 / 2.52 s | Elapsed : 2.00 / 3.00 s

I have a very simple schematic with waittime going out to an output
marker.

waittime:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity waittime is
Port ( z : out std_logic);
end waittime;

architecture Behavioral of waittime is

begin
z <= '1' after 500000000 ns;

z <= '0' after 500000000 ns;

end Behavioral;


I am using a CR-II c256 and ISE 6.3.03i.

Any help would be appreciated!

Thanks,
Brian

 

I am actually wanting the cpld to toggle the signal for real not for
just simulation. What should I use instead of "after"? How should I
toggle it so I do not get the multisource error?

Thanks in advance,
Brian