G
Giox
Guest
Hello everybody, I have some doubts about how to code in Verilog.
In fact I use the Xilinx tools ISE 7.1, and I learn Verilog with the
book "VerilogŽ HDL: A Guide to Digital Design and Synthesis, Second
Edition".
In the manual of Xilinx it seems that using an high level description
it's possible to achieve optimal performances.
For example it seems that the use of carry logic by inferring XORCY,
MUXCY, and MULT_AND can be achieved through a behavioral description.
However I would like to know your advice about that, that is it's better
to use a behavioral description or a dataflow one? The book says that's
better to use a RTL description, but I don't understand if, for example,
implementing at RTL level a CLA the synthetizer will be able to infer
the MULT_AND port or if I have to specify its use...
Moreover can you suggest me some good book about digital design, to
better understand the possible implementation of multiplier, adder etc?
Thanks a lot, Giovanni
--
My Email is correct
In fact I use the Xilinx tools ISE 7.1, and I learn Verilog with the
book "VerilogŽ HDL: A Guide to Digital Design and Synthesis, Second
Edition".
In the manual of Xilinx it seems that using an high level description
it's possible to achieve optimal performances.
For example it seems that the use of carry logic by inferring XORCY,
MUXCY, and MULT_AND can be achieved through a behavioral description.
However I would like to know your advice about that, that is it's better
to use a behavioral description or a dataflow one? The book says that's
better to use a RTL description, but I don't understand if, for example,
implementing at RTL level a CLA the synthetizer will be able to infer
the MULT_AND port or if I have to specify its use...
Moreover can you suggest me some good book about digital design, to
better understand the possible implementation of multiplier, adder etc?
Thanks a lot, Giovanni
--
My Email is correct