Need PCIe Help

[Rob Gaddi]

Hey all --

I've got a client breathing down my neck, asking if there's anything
that can be done to accelerate a design we're doing for them. The one
piece of the design that's really going to take me some serious time is
figuring out the PCI Express nonsense.

The target FPGA is an Arria II GX. We plan to implement an 8 lane, Gen
1 PCIe link over a cable back to the host processor. I was thinking of
using the PLDA EZDMA core to try to speed the design up; they're hoping
to have this entire thing up and running in weeks.

Does anyone have any experience with PCIe on the Arria II GX, either
with the help of someone's expensive IP core or just going straight into
Altera's hard IP block?

Thanks,
Rob

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Gabor]

On Apr 12, 9:21 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:

Hey all --

I've got a client breathing down my neck, asking if there's anything
that can be done to accelerate a design we're doing for them.  The one
piece of the design that's really going to take me some serious time is
figuring out the PCI Express nonsense.

The target FPGA is an Arria II GX.  We plan to implement an 8 lane, Gen
1 PCIe link over a cable back to the host processor.  I was thinking of
using the PLDA EZDMA core to try to speed the design up; they're hoping
to have this entire thing up and running in weeks.

Does anyone have any experience with PCIe on the Arria II GX, either
with the help of someone's expensive IP core or just going straight into
Altera's hard IP block?

Thanks,
Rob

--
Rob Gaddi, Highland Technology
Email address is currently out of order

I've used the PLDA core on a Virtex 5 LXT, but as I understand
the user interface should be similar. My only comment is that
the core itself is quite complex, and the documentation seemed
to be written more for the core designers than for the core users.
Their technical support is quite helpful (and quite necessary
given the documentation), and still I found I needed to start by
hacking on their demo program to get my system up and running
in any reasonable amount of time. Once you get a handle
on the user interface, it's much easier than writing all of
the transport layer stuff yourself, assuming what you really
want is DMA. Multichannel works fine. We bought it mainly
for the scatter/gather feature, and then the software guys
decided to use kernel contiguous memory anyway...

I'm not sure what Altera provides for device drivers with their
own demo apps. The PLDA stuff is much better than the
Xilinx offerings. Also we may be doing a port to Altera on
this same project, so it's good to have a core available
on both platforms.

Regards,
Gabor

 

[Rob Gaddi]

On 4/13/2011 9:51 AM, steve wrote:

On Apr 12, 9:21 pm, Rob Gaddi<rga...@technologyhighland.com> wrote:
Hey all --

I've got a client breathing down my neck, asking if there's anything
that can be done to accelerate a design we're doing for them. The one
piece of the design that's really going to take me some serious time is
figuring out the PCI Express nonsense.

The target FPGA is an Arria II GX. We plan to implement an 8 lane, Gen
1 PCIe link over a cable back to the host processor. I was thinking of
using the PLDA EZDMA core to try to speed the design up; they're hoping
to have this entire thing up and running in weeks.

Does anyone have any experience with PCIe on the Arria II GX, either
with the help of someone's expensive IP core or just going straight into
Altera's hard IP block?

Thanks,
Rob

--
Rob Gaddi, Highland Technology
Email address is currently out of order

If you want it fast on Altera, consider using their SOPC builder
tool.

SOPC Builder is a GUI based system builder similar to Xilinx EDK. I
have a design running on a Stratix IV GX which uses a 4 lane PCIe core
(limited by my v9.1 software, their web site shows x8 available now
for SOPC use) and an SG-DMA core both of which are available in SOPC
builder. Also using SOPC builder, I converted my custom logic into a
custom SOPC builder component. The speed advantage comes from having
the SOPC builder tool generate all the system interconnect fabric
(arbitration and burst logic, chip enables, intermediate addressing,
etc.) rather than you having to write it. Obviously, the design isn't
fully optimized since it is auto-generated but if you can live with
the performance you get, it saves a lot of time.

Note that there may be some other feature limitations in the stock
SOPC Builder cores which aren't present if you write your entire
design by hand, so check the doc's to make sure you're OK with them.
For reference, in a previous design for a Virtex 5 which used a PCIe
core, it took me an extra couple of months to create the PCIe core
user interface logic by hand (I guess that also included my PCIe
learning curve).

Regards,
Steve

Love to, but the PCIe core at 8 lanes on the Arria II GX only supports
Avalon-ST, not the Avalon-MM that you need to be able to plug into SOPC
Builder. Practically every other configuration is available, but that
one little corner is SOL.

I originally thought about writing my own bridge to go from the
transaction layer packets that come across the ST interface to an SOPC
master, but non-aligned accesses can generate some very uncomfortable
packets that would probably take me a week and change to get thought
out, written, and tested.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[steve]

On Apr 12, 9:21 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:

Hey all --

I've got a client breathing down my neck, asking if there's anything
that can be done to accelerate a design we're doing for them.  The one
piece of the design that's really going to take me some serious time is
figuring out the PCI Express nonsense.

The target FPGA is an Arria II GX.  We plan to implement an 8 lane, Gen
1 PCIe link over a cable back to the host processor.  I was thinking of
using the PLDA EZDMA core to try to speed the design up; they're hoping
to have this entire thing up and running in weeks.

Does anyone have any experience with PCIe on the Arria II GX, either
with the help of someone's expensive IP core or just going straight into
Altera's hard IP block?

Thanks,
Rob

--
Rob Gaddi, Highland Technology
Email address is currently out of order

If you want it fast on Altera, consider using their SOPC builder
tool.

SOPC Builder is a GUI based system builder similar to Xilinx EDK. I
have a design running on a Stratix IV GX which uses a 4 lane PCIe core
(limited by my v9.1 software, their web site shows x8 available now
for SOPC use) and an SG-DMA core both of which are available in SOPC
builder. Also using SOPC builder, I converted my custom logic into a
custom SOPC builder component. The speed advantage comes from having
the SOPC builder tool generate all the system interconnect fabric
(arbitration and burst logic, chip enables, intermediate addressing,
etc.) rather than you having to write it. Obviously, the design isn't
fully optimized since it is auto-generated but if you can live with
the performance you get, it saves a lot of time.

Note that there may be some other feature limitations in the stock
SOPC Builder cores which aren't present if you write your entire
design by hand, so check the doc's to make sure you're OK with them.
For reference, in a previous design for a Virtex 5 which used a PCIe
core, it took me an extra couple of months to create the PCIe core
user interface logic by hand (I guess that also included my PCIe
learning curve).

Regards,
Steve