Need help with using inout (bi-dir) in VHDL for Xilinx FPGA

[sg]

Hi All -

I am trying to use bi-directional I/O pin in VHDL (inout). When I run it
through the Xilinx ISE, in the Pad report it converts the inout pin as
output. Is there any sample example/code which I can try to make sure I am
not writing something incorrect. Thanks.

- Sunil

 

[A Beaujean]

"sg" <sunil.k.gupta@intel.com> wrote in message news:<c4tc2u$blc$1@news01.intel.com>...

Hi All -

I am trying to use bi-directional I/O pin in VHDL (inout). When I run it
through the Xilinx ISE, in the Pad report it converts the inout pin as
output. Is there any sample example/code which I can try to make sure I am
not writing something incorrect. Thanks.

- Sunil

Are you sure you use the pin for internal logic ?