S
Stephen Williams
Guest
Hi all,
I've received a bug report from a user who wants Icarus Verilog to be
able to parse statements like this (within specify blocks):
$setup (posedge dudu[0], edge[0x,01,1x] C &&& (dude === 1'b1),
hu, ooooh12_0);
In particular, note the "edge[0x,01,1x]", in the place where I expect
a posedge or negedge. I can guess what this means, but I need more
information. Like, what is the syntax for it? (It is not part of the
IEEE standard 1364 as far as I can tell.) Which tools support it?
How widespread is it? How do I handle it lexically? I can't just make
"edge" a keyword, that'll break valid Verilog programs. It appears
that "edge[...]" may be a lexical token, but "edge[01]" is for example
also perfectly valid Verilog that would break if I did that.
This is going to be a tough nut, any pointers will be much appreciated.
Thanks,
I've received a bug report from a user who wants Icarus Verilog to be
able to parse statements like this (within specify blocks):
$setup (posedge dudu[0], edge[0x,01,1x] C &&& (dude === 1'b1),
hu, ooooh12_0);
In particular, note the "edge[0x,01,1x]", in the place where I expect
a posedge or negedge. I can guess what this means, but I need more
information. Like, what is the syntax for it? (It is not part of the
IEEE standard 1364 as far as I can tell.) Which tools support it?
How widespread is it? How do I handle it lexically? I can't just make
"edge" a keyword, that'll break valid Verilog programs. It appears
that "edge[...]" may be a lexical token, but "edge[01]" is for example
also perfectly valid Verilog that would break if I did that.
This is going to be a tough nut, any pointers will be much appreciated.
Thanks,