need help with QAM demodulation

[lomtik]

Hi,
I am thinking of writing VHDL code for QAM signal demodulation and
have several questions on carrier and timing recovery as well as bit
detection. I have done some bpsk simulation already, but having
trouble with exporting to higher order modulation.

For carrier recovery block I think I can use open loop recovery
scheme. For example, BPSK signal is squared to recover the carrier at
twice the frequency. Then I can do frequency division and LPF the
output to produce a single tone carrier. Then I multiply the carrier
with the delayed input signal. From the result it's possible to do bit
decisions from sign of the signal at given recovered symbol clock
locations.
I think it's possible to extend this method to QPSK by squaring input
signal twice. But the multiply 90deg shifted versions of the recovered
carrier by Q channel instead. Do the same bit decisions and combine
both channels at twice the speed.

This method could be troublesome. Any other ideas? maybe different
type of carrier recovery?
What should I do with cases when recovered carrier (i.e. cos) is
multilplied by sin(x) and -sin(x). This would give me .5*sin(2x)
centered at 0 hard to do decide whether it's 1, -1 or signal from
another channel.


Thanks for any help!

 

[lomtik]

bump

(I am new to groups, hope the messages are refreshed forum-style)

 

[Paul Uiterlinden]

lomtik wrote:

bump

(I am new to groups, hope the messages are refreshed forum-style)

No, it is not.

Your question seems not to be related to VHDL at all, hence no answer.

Paul.

 

[lomtik]

Thanks

Actually, I was hoping to get some insight into bridging analog theory
with digital fpga implementation. For example, in analog domain, it's
easy to mix signals, but in FPGA multiplication, it's better to use
some other tricks if possible to avoid generation of huge amount of
logic.

I figured out something duing this time. QAM signal of 16, 64 etc.. can
be generated using bpsk signals on 2 channels. From sign it's possible
to tell whether it's one or zero, and from magnitude - the rest of
constellation info.

Now, the question is how to correctly distinguish magnitudes of bpsk
signals.
I was thinking, once synchronized, take specific number of samples for
each channel per period, track the magnitudes and output the maximum,
holding it for the next symbol period T. Knowing that information, I
can compare the maximum value to some thresholds to determine which bit
does it represent.
I am not sure if this is common approach and the most easiest for fpga.
How do you think?