need help with code

[Ilan]

Hello,
I'm new to VERILOG.
this is my second code and it doesn't seem to work.
I'm trying to generate clock_pulse of frequency 5mHz and start_pulse each
2500 clock_pulses
with setup time and hold time related to clock_pulse (i.e start_pulse is
supposed to appear before clock_pulse drops and to finish after clock_pulse
dropped).
Simulation looks OK but when trying to synthesize in FPGA I keep getting the
same clock_pulse signal
of 0.5mHz regardless of which CLOCKDIV I use.
Am I doing something wrong?
Please help!

Thanx,
Ilan



module shortpic
(
clk,
reset,
start_pulse,
clock_pulse

);



parameter CLOCKDIV = 11'b00000000011;
parameter TINT = 13'b0100111000100;

input clk;
input reset;
output start_pulse;
output clock_pulse;


reg [10:0] Clock_Counter;
reg [12:0] Sp_Counter,Sp_En_Counter;
reg start_pulse;
reg clock_pulse;
reg start_pulse_enable;





always @ (posedge clk or negedge start_pulse_enable)
begin
if (start_pulse_enable == 1'b0)
begin //begin two
start_pulse <= 1'b0;
Sp_Counter = 'b0;
end
else
begin
Sp_Counter = Sp_Counter + 1;
if ((Sp_Counter == (CLOCKDIV-1)) || (Sp_Counter == (CLOCKDIV+1) ))

begin
start_pulse <= ~start_pulse;
end
if (Sp_Counter == (CLOCKDIV+3))
begin
Sp_Counter = 'b0;
end
end
end


always @ (posedge clk or negedge reset)
begin
if (reset == 'b0)
begin
Clock_Counter = 'b0;
clock_pulse <= 'b0;
end
else
begin
if (Clock_Counter == CLOCKDIV)
begin
Clock_Counter = 'b0;
clock_pulse <= ~clock_pulse;
end
else
Clock_Counter = Clock_Counter + 1;
end
end

always @ (posedge clock_pulse or negedge reset)
begin
if (reset == 1'b0)
begin
start_pulse_enable <= 1'b0;
Sp_En_Counter = 'b0;
end
else
begin
if (Sp_En_Counter == TINT)
begin
start_pulse_enable <= 1'b1;
Sp_En_Counter = 'b0;
end
else
begin
start_pulse_enable <= 1'b0;
Sp_En_Counter = Sp_En_Counter + 1;
end
end
end

endmodule