need help! Verilog compile error on modelSim

[thomasc]

Hi,
I'm stuck in a strange situation question and need halp.

From a Verilog module, called 'a.v', I instantiated another module, 'b.v'.
While compiling 'a.v' using ModelSim 5.8c, I got an error message as
follows:

# ** Error: C:/ ..... a.v(28): Undefined variable: b

I don't understand it because 'b.v' module is in the same project with
'a.v' and it has passed its own testbench. and it seems that 'a.v' does
not "know" that 'b.v' is another module.

is there anyone who've had same situation?
any comment on this will be appreciated.

Thanks,
Thomas

 

[newman]

"thomasc" <altecsplinter@hotmail.com> wrote in message
news:b8ad0808c0ba906a0e98dfc5d7e44bf1@localhost.talkaboutprogramming.com...

Hi,
I'm stuck in a strange situation question and need halp.

From a Verilog module, called 'a.v', I instantiated another module, 'b.v'.
While compiling 'a.v' using ModelSim 5.8c, I got an error message as
follows:

# ** Error: C:/ ..... a.v(28): Undefined variable: b

I don't understand it because 'b.v' module is in the same project with
'a.v' and it has passed its own testbench. and it seems that 'a.v' does
not "know" that 'b.v' is another module.

is there anyone who've had same situation?
any comment on this will be appreciated.

Thanks,
Thomas

Thomas,
I would suggest that you look at some of the Modelsim examples. like
../examples/vidpoker/ If the vidpoker runs OK, then I would guess that your
installation might be OK, and perhaps you need to mimick the example more
closely.

Regards
Newman
>

 

The names 'a.v' and 'b.v' look to me like file names,
rather than module names.

 

[Paul Uiterlinden]

thomasc wrote:

From a Verilog module, called 'a.v', I instantiated another module, 'b.v'.
While compiling 'a.v' using ModelSim 5.8c, I got an error message as
follows:

# ** Error: C:/ ..... a.v(28): Undefined variable: b

To me this just looks like a typo in your code. Without actually seeing
the code there's not much more that I can say.

Paul.