Need Help: trisate problem

[samtee]

Hi,
Here is my verilog code (Xilinx webpack 8.01 sp3)

module Count(input reset, input clock, output wire [7:0]v,output
reg[7:0] c);

reg temp;

reg incC;
always@(posedge clock)
begin
if(reset) begin c<=0; end
else
begin
if(incC) begin
c<=c+5;

end

end
end


assign v= temp?8'hZ:c;
integer ps,ns;
always@(posedge clock)
if(reset)ps<=0; else ps<=ns;
always@*
case(ps)
0: begin temp=0; incC=1; ns=1; end
1: begin temp=1; incC=0; ns=2; end
2: begin temp=1; incC=0; ns=3; end
3: begin temp=0; incC=0; ns=0; end
endcase
endmodule

I should have high impedance (Z) anytime that temp eq. 1.
However, when I simulate using MicroSIM XE III 6.0d (free version), I
got X's where bits suppose to be 1.

Please help. (Sorry about my English)
Thank you,
Sam

 

[Michael]

Are you sure you have reset while clock is ticking?

 

[samtee]

Michael wrote:

Are you sure you have reset while clock is ticking?

Yes.
I suspect that it is because xst try to replace tristate logic with
other logic.
Thank you for your respond.
sam

 

[Michael]

Next time try to define 'temp' as output from FF.

 

[Steve Pope]

Another thing you can try is the "tranif0" and/or "tranif1"
primitives. This is an alternatize to trying to assign
"Z" to a node.

Steve