need help regarding block ram in verilog

[m2star]

hi all..........!!
hope you are fine, i am using a dual port BRAM for my project
(on Spartan 3), i write the code for this dual port bram according to
the given code in datasheet of the spartan board. its working properly
for simulation, i have a synthesis code (using .coe file) properly
working for single port Bram but now i need to write a code for the
dual port bram to synthesis can anyone
help.....................????????............

 

[johnp]

On Apr 8, 12:46 am, m2star <m2s...@hotmail.com> wrote:

hi all..........!!
      hope you are fine, i am using a dual port BRAM for my project
(on Spartan 3), i write the code for this dual port bram according to
the given code in datasheet of the spartan board. its working properly
for simulation, i have a synthesis code (using .coe file) properly
working for single port Bram but now i need to write a code for the
dual port bram to synthesis can anyone
help.....................????????............

I believe the XST user guide has verilog templates for implying all
sorts
of BRAM variations. If you do this, I believe you will either need to
use initial statements or $readmemh to initialize the brams.

There are threads describing the limitations of Xilinx's
implementation
of $readmemh.

Good luck,

John Providenza