Need help : proc_i = vpi_iterate(vpiProcess, mod_h);

C

Cricket Fan

Guest
Any thoughts on why proc_i is always NULL?

/*partial listing for check_code_calltf()*/

task_h = vpi_handle(vpiSysTfCall, NULL);
/*get handle to scope from where task was called*/
scope_h = vpi_handle(vpiScope, task_h);
mod_h = scope_h; //scope is top-level module.
proc_i = vpi_iterate(vpiAlways, mod_h);

---verilog listing----
`timescale 1ns/100ps
module plitest (a,b,q,ck,r);
input a,b,ck,r;
output q;

reg q, q_bar;
wire d;

initial
$check_code();

assign d = a | b;

always@(posedge ck or negedge r)
if(!r)
q <= 1'b0;
else
q <= d;

always@(q)
q_bar = ~q;

endmodule
---------end verilog list----------

TIA,
-sanjay
 
Hi Sanjay,
You have used:
scope_h = vpi_handle(vpiScope, task_h);

instead you should use

scope_h = vpi_handle(vpiModule, task_h);


I haven't tested this particular code, but have done similar stuff in
the past - this should work.

Let me know if it doesn't help.

Regards,
Ajeetha
http://www.noveldv.com
fpgabuilder-news@yahoo.com (Cricket Fan) wrote in message news:<55814a3c.0410031559.7504077d@posting.google.com>...
Any thoughts on why proc_i is always NULL?

/*partial listing for check_code_calltf()*/

task_h = vpi_handle(vpiSysTfCall, NULL);
/*get handle to scope from where task was called*/
scope_h = vpi_handle(vpiScope, task_h);
mod_h = scope_h; //scope is top-level module.
proc_i = vpi_iterate(vpiAlways, mod_h);

---verilog listing----
`timescale 1ns/100ps
module plitest (a,b,q,ck,r);
input a,b,ck,r;
output q;

reg q, q_bar;
wire d;

initial
$check_code();

assign d = a | b;

always@(posedge ck or negedge r)
if(!r)
q <= 1'b0;
else
q <= d;

always@(q)
q_bar = ~q;

endmodule
---------end verilog list----------

TIA,
-sanjay
 
Hello Ajeetha,

Thank you for your feedback. FYI - Modelsim 6.0 does not support
iterating through the processes.
By using s_vpi_error_info and vpi_chk_error(), it produces an internal
error which says something to the effect of - cannot get to processes
from module.

Bummer!
 

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