C
Cricket Fan
Guest
Any thoughts on why proc_i is always NULL?
/*partial listing for check_code_calltf()*/
task_h = vpi_handle(vpiSysTfCall, NULL);
/*get handle to scope from where task was called*/
scope_h = vpi_handle(vpiScope, task_h);
mod_h = scope_h; //scope is top-level module.
proc_i = vpi_iterate(vpiAlways, mod_h);
---verilog listing----
`timescale 1ns/100ps
module plitest (a,b,q,ck,r);
input a,b,ck,r;
output q;
reg q, q_bar;
wire d;
initial
$check_code();
assign d = a | b;
always@(posedge ck or negedge r)
if(!r)
q <= 1'b0;
else
q <= d;
always@(q)
q_bar = ~q;
endmodule
---------end verilog list----------
TIA,
-sanjay
/*partial listing for check_code_calltf()*/
task_h = vpi_handle(vpiSysTfCall, NULL);
/*get handle to scope from where task was called*/
scope_h = vpi_handle(vpiScope, task_h);
mod_h = scope_h; //scope is top-level module.
proc_i = vpi_iterate(vpiAlways, mod_h);
---verilog listing----
`timescale 1ns/100ps
module plitest (a,b,q,ck,r);
input a,b,ck,r;
output q;
reg q, q_bar;
wire d;
initial
$check_code();
assign d = a | b;
always@(posedge ck or negedge r)
if(!r)
q <= 1'b0;
else
q <= d;
always@(q)
q_bar = ~q;
endmodule
---------end verilog list----------
TIA,
-sanjay