NEED HELP: multiply and divide with integer in VHDL

hi all,

I'm new with VHDL. In my code, i have to calculate, like:

value_output := (buff00 - min) * 255 / max;

in which, these variables are declared as integers.

variable max: integer;
variable min: integer;
variable buff00: integer;
variable value_output: integer;

I've got no syntax error. But when i try to synthesize, i got this
error:

Operator <DIVIDE> must have constant operands or first operand must be
power of 2

HOw can I fix it?

Thks so much, it's urgent!
Kha

 

[David Bishop]

ledinhkha@gmail.com wrote:

hi all,

I'm new with VHDL. In my code, i have to calculate, like:

value_output := (buff00 - min) * 255 / max;

in which, these variables are declared as integers.

variable max: integer;
variable min: integer;
variable buff00: integer;
variable value_output: integer;

I've got no syntax error. But when i try to synthesize, i got this
error:

Operator <DIVIDE> must have constant operands or first operand must be
power of 2

HOw can I fix it?

Two ways:
1) Use a different synthesis tool. Only primitive ones don't support
"divide".

2) You can do a divide two ways. Either a subtraction tree or a Newton
Raphson. You can find examples of both in my floating point packages at:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html
Look for a function called "short_divide". You will have to expand it
to take a numerator of a variable MSB.

 

[Thomas Stanka]

Hi,

ledinhkha@gmail.com schrieb:

I'm new with VHDL. In my code, i have to calculate, like:

value_output := (buff00 - min) * 255 / max;

in which, these variables are declared as integers.

variable max: integer;
variable min: integer;
variable buff00: integer;
variable value_output: integer;

I've got no syntax error. But when i try to synthesize, i got this
error:

Operator <DIVIDE> must have constant operands or first operand must be
power of 2

HOw can I fix it?

By just rereading my answer on your question three days ago and doing
the task to agreed to do: read about dividers in HW (and understand
what you read).
We all will answer your concrete question that likely will arise, but
this newsgroup is no online-task-solver.

A divider is a bit more complex than just an AND. You have a lot of
posibillities to implement a divider and each has its own limitations
and goodies, so you need to be a bit more precise to the synthesis. Of
course your right when saying a synthesis tool should always infer a
simple parallel divider for this code and it should be up to you to
replace the parallel divider by a better sollution when necessary, but
in real designs there is more harm done this way, than telling division
can't be done that way.

A simple sollution would be to search a divider core that fits for your
needs Xilinx provides a divider in coregen, I gues every other Vendor
as well. Opencore would be second place to have a look.

Your code needs a 32-Bit divider. I'm not sure if you need a 32 bit
divider, but you will face some problems with a parallel divider with
32 bit width.

bye Thomas