need help in modelling

Could anyone help on modelling the following circuits in verilog?
Thanks in advance!

A)
| __
| CP
| |
| ___O___
| | |
| ---O| INV |--------
| | |_______| |
| | | |
| | CP |
| | |
| | |
| CP | |
| | | |
| ___O___ | _______ |
| | | | | | |
| D---| INV |O----|-----| NOR |O------|
| |_______| X R--| | Y
| | |_______|
| __
| CP




B)

| __
| CP
CP
| | _
|
| ___O___ Q
___O___
| | | | |
|
| ----O| INV |-------- |----O|
INV |----
| | |_______| | |
|_______| |
| | | | |
| |
| | CP | |
__ |
| | | |
CP |
| | | __ |
|
| CP | | CP |
|
| | | | | |
|
| ___O___ | _______ | ___O___ |
_______ |
| | | | | | | | | | |
| |
| D---| INV |O----|-----| NOR |O------|--------| INV |O--|---|
NOR ||O-----|---- Q
| |_______| X1 R--| | Y |_______| X2 R-|
|
| | |_______| |
|_______|
| __ CP
| CP

 

[m]

On 16 Jan 2005 18:30:15 -0800, triste@myrealbox.com wrote:

Could anyone help on modelling the following circuits in verilog?
Thanks in advance!

The B schematic is not very clear but it seems like a master-slave FF
made from two A modules. The A module is an async reset latch.

 

cant read the schematics properly.