Need help in linear scaling of standard cell layout from 130

[nvss]

Hi All,
I am interested in linear scaling of standard cell layouts from 130nm
to 90nm and I am trying to automate it through skill.
I scaled every shape in the layout by the scale factor (90/130) but
then realised it wouldnt work.

Could any of you suggest how I could go about solving this problem?

Thanks,
Karthikeyan Neelakanda

 

[Bernd Fischer]

Two products who can do this, I know:
http://www.sagantec.com/migrationandreuse.html
http://www.cadence.com/products/custom_ic/virtuoso_layout_migrate/index.aspx

I'm not sure if this can be sucessfuly done with SKILL or a physical
verification toll, especial if most of the technologies are not scaled
linear over all layers.

Bernd

nvss wrote:

Hi All,
I am interested in linear scaling of standard cell layouts from 130nm
to 90nm and I am trying to automate it through skill.
I scaled every shape in the layout by the scale factor (90/130) but
then realised it wouldnt work.

Could any of you suggest how I could go about solving this problem?

Thanks,
Karthikeyan Neelakanda

 

[gerry@ictooling.com]

On Jan 29, 4:16 pm, "nvss" <karthik...@gmail.com> wrote:

Hi All,
I am interested in linear scaling of standard cell layouts from 130nm
to 90nm and I am trying to automate it through skill.
I scaled every shape in the layout by the scale factor (90/130) but
then realised it wouldnt work.

Could any of you suggest how I could go about solving this problem?

Thanks,
Karthikeyan Neelakanda

Why will it not work?
The problem you have is that you likely need to apply a different set
of scaling
and snapping properties to each and every different kind of structure.

One trick is to write yourself a feature rich scaling/snapping tool.
Then you need to run this on a few of your basic structures.

(i.e. in Std cells, we typically have a min. transistor size that we
want.
The gate width is almost always drawn to a minimum ( or nominal!)
size.

The gate length is usually constrained to a ratioed amount of the
width.

Ne next problem is that Via/Contact structures in these processes
typically have
one size, so they need to to be scaled/snapped properly.

Also some rules will not scale well, so some "generation" will need to
be made.
(i.e. let say that after a 130->90 conversion, the gate overlap is too
small, then grow this!)

Another Assumption is that the relative drive strength N vs P is the
same or this must be adjusted in CMOS.

Analog devices need to be tweeked so that the required physical
parameters are preserved. ( i.e. Caps, Diodes, Resistors )

It can be done, but is not trivial and any flow that I have done was
never 100% automated. ( The last tweeks were typically easier to hand
fix rather than automate.)

I have done this with several libraries ...
( i.e. 250nm bicmos -> 180nm bicmos different fab for a CML logic
library )
( 180nm MOSIS cmos 1.2v lib -> 180u 3.3v lib )
( 65nm custom lib -> DFM hardened 65nm custom lib )
etc.

YMMV