Need guidance for NEOcell PDK

[gte558w]

Hi,

I looking for any guidance to generate Process Design Kit for NEOcell.

Thanks

 

[John Gianni]

gte558w wrote:

I looking for any guidance to generate Process Design Kit for NEOcell.

Probably way more powerful than what you are looking for ... but, for
the record, Cadence sells a software product called "PAS" (PDK
Automation System) which automatically generates complete PDKs (process
design kits), including NeoConfig technology files ... using as an
input graphically drawn geometrical information about the process.

Nothing generates a CDK (complete design kit) ... yet ... where a CDK
is simply defined as everything you need to build the given chip in the
given flow. For example, a CDK for a Cadence-based flow would include
technology files for NeoCell, Virtuoso Layout Migrate, CeltIC, Assura,
Spectre, First Encounter, VoltageStorm, Virtuoso Chip Assembly Router,
Virtuoso Turbo ToolBox, etc.

Very few foundries supply a CDK.

The closest CDK I know of (NCSU notwithstanding) is that which is
supplied today by Tower Semiconductor as their downloadable AMS
reference flow. Tower actually fab'd and tested the Cadence Eaglet
garage-door receiver test chip and supplies not only the complete chip
with their downloads, but, they also supply the complete design kit
containing everything needed (including the standard cells and various
software configuration files) for the stated flow.

IMHO, if foundries supplied a Complete Design Kit, you wouldn't need to
ask this question.
</soapbox>

John Gianni
--
Nothing stated here is prior reviewed nor prior sanctioned by my
employer!