need desperate help!

F

filippo

Guest
I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

facts:

- FPGA SPARTAN II xc2s100-5pq208
- Xilinx webpack ISE + modelsim
- uP: AVRmega163

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).

of the 10+ modules one seems to be the most troublesome, our
IO_control, here is the code ,please help.

---------------------------------------------------------------------------------
module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);

input ALE;

input NWR;

input clk;

input NRD;

input DIR;

input [7:0] MIN;

input [7:0] MAX;

inout [7:0] DA;

output [7:0] SEL;

output [7:0] TYPEFIL;

output [7:0] AMPLIF;

output [7:0] DIVFRQ;

parameter uno = 8'b0000_0001;



reg [7:0] ADDR_REG;

reg [7:0] DO_REG;

reg [7:0] SEL_REG=uno;

reg [7:0] TYPEFIL_REG=uno;

reg [7:0] AMPLIF_REG=uno;

reg [7:0] DIVFRQ_REG=uno;





assign SEL = SEL_REG;

assign TYPEFIL = TYPEFIL_REG;

assign AMPLIF = AMPLIF_REG;

assign DIVFRQ = DIVFRQ_REG;



assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;



always @ (posedge clk)

begin

if (ALE) ADDR_REG <= DA;

if (~NWR)

case (ADDR_REG)

8'b0000_0001 : SEL_REG <= DA;

8'b0000_0010 : TYPEFIL_REG <= DA;

8'b0000_0100 : AMPLIF_REG <= DA;

8'b0000_1000 : DIVFRQ_REG <=DA;

default DO_REG <= 8'b1111_1111;

endcase

if (~NRD)

case (ADDR_REG)

8'b0000_0001 : DO_REG <= SEL_REG;

8'b0000_0010 : DO_REG <= TYPEFIL_REG;

8'b0000_0100 : DO_REG <= AMPLIF_REG;

8'b0000_1000 : DO_REG <= DIVFRQ_REG;

8'b0001_0000 : DO_REG <= MIN;

8'b0010_0000 : DO_REG <= MAX;

default DO_REG <= 8'b1111_1111;

endcase

end



endmodule
 
filippo wrote:

I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

facts:

- FPGA SPARTAN II xc2s100-5pq208
- Xilinx webpack ISE + modelsim
- uP: AVRmega163

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).
Click to expand...
Did you simulate the pure Verilog code or the back-annotated code
(i.e. after synthesis)? You know, not every formally valid code
will be correctly synthesized. I don't know Verilog and so I cannot
give comments to your code. So you should check whether you described
your problem using the right coding conventions.

Also check whether you got some timing problems.

Regards,
Mario
 
Did you apply timing constraints to the design ... does your design
meet the timing constraints. As a minimum you should have three
bassic constraints applied ...
FFS to FFS
FFS to PADs
PADs to FFS

Mike

"filippo" <filippdavid@yahoo.com> wrote in message
news:18add487.0402060204.340e7b39@posting.google.com...
I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

facts:

- FPGA SPARTAN II xc2s100-5pq208
- Xilinx webpack ISE + modelsim
- uP: AVRmega163

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).

of the 10+ modules one seems to be the most troublesome, our
IO_control, here is the code ,please help.

--------------------------------------------------------------------------
-------
module
IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);

input ALE;

input NWR;

input clk;

input NRD;

input DIR;

input [7:0] MIN;

input [7:0] MAX;

inout [7:0] DA;

output [7:0] SEL;

output [7:0] TYPEFIL;

output [7:0] AMPLIF;

output [7:0] DIVFRQ;

parameter uno = 8'b0000_0001;



reg [7:0] ADDR_REG;

reg [7:0] DO_REG;

reg [7:0] SEL_REG=uno;

reg [7:0] TYPEFIL_REG=uno;

reg [7:0] AMPLIF_REG=uno;

reg [7:0] DIVFRQ_REG=uno;





assign SEL = SEL_REG;

assign TYPEFIL = TYPEFIL_REG;

assign AMPLIF = AMPLIF_REG;

assign DIVFRQ = DIVFRQ_REG;



assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;



always @ (posedge clk)

begin

if (ALE) ADDR_REG <= DA;

if (~NWR)

case (ADDR_REG)

8'b0000_0001 : SEL_REG <= DA;

8'b0000_0010 : TYPEFIL_REG <= DA;

8'b0000_0100 : AMPLIF_REG <= DA;

8'b0000_1000 : DIVFRQ_REG <=DA;

default DO_REG <= 8'b1111_1111;

endcase

if (~NRD)

case (ADDR_REG)

8'b0000_0001 : DO_REG <= SEL_REG;

8'b0000_0010 : DO_REG <= TYPEFIL_REG;

8'b0000_0100 : DO_REG <= AMPLIF_REG;

8'b0000_1000 : DO_REG <= DIVFRQ_REG;

8'b0001_0000 : DO_REG <= MIN;

8'b0010_0000 : DO_REG <= MAX;

default DO_REG <= 8'b1111_1111;

endcase

end



endmodule
Click to expand...
 
Hi Filippo,

I assume the clk signal in your code is the AVR clock. You should implement
the interface asynchronously and when you have the data in the FPGA
synchronize it to whatever clock you have there. This is an excerpt from the
ATmega162L datasheet:

"Note that the XMEM interface is asynchronous and that the waveforms in the
figures
below are related to the internal system clock. The skew between the
internal and external
clock (XTAL1) is not guaranteed (it varies between devices, temperature, and
supply
voltage). Consequently, the XMEM interface is not suited for synchronous
operation."

Regards,
-- Georgi

"filippo" <filippdavid@yahoo.com> wrote in message
news:18add487.0402060204.340e7b39@posting.google.com...
I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

facts:

- FPGA SPARTAN II xc2s100-5pq208
- Xilinx webpack ISE + modelsim
- uP: AVRmega163

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).

of the 10+ modules one seems to be the most troublesome, our
IO_control, here is the code ,please help.

--------------------------------------------------------------------------
-------
module
IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);

input ALE;

input NWR;

input clk;

input NRD;

input DIR;

input [7:0] MIN;

input [7:0] MAX;

inout [7:0] DA;

output [7:0] SEL;

output [7:0] TYPEFIL;

output [7:0] AMPLIF;

output [7:0] DIVFRQ;

parameter uno = 8'b0000_0001;



reg [7:0] ADDR_REG;

reg [7:0] DO_REG;

reg [7:0] SEL_REG=uno;

reg [7:0] TYPEFIL_REG=uno;

reg [7:0] AMPLIF_REG=uno;

reg [7:0] DIVFRQ_REG=uno;





assign SEL = SEL_REG;

assign TYPEFIL = TYPEFIL_REG;

assign AMPLIF = AMPLIF_REG;

assign DIVFRQ = DIVFRQ_REG;



assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;



always @ (posedge clk)

begin

if (ALE) ADDR_REG <= DA;

if (~NWR)

case (ADDR_REG)

8'b0000_0001 : SEL_REG <= DA;

8'b0000_0010 : TYPEFIL_REG <= DA;

8'b0000_0100 : AMPLIF_REG <= DA;

8'b0000_1000 : DIVFRQ_REG <=DA;

default DO_REG <= 8'b1111_1111;

endcase

if (~NRD)

case (ADDR_REG)

8'b0000_0001 : DO_REG <= SEL_REG;

8'b0000_0010 : DO_REG <= TYPEFIL_REG;

8'b0000_0100 : DO_REG <= AMPLIF_REG;

8'b0000_1000 : DO_REG <= DIVFRQ_REG;

8'b0001_0000 : DO_REG <= MIN;

8'b0010_0000 : DO_REG <= MAX;

default DO_REG <= 8'b1111_1111;

endcase

end



endmodule
Click to expand...
 
filippo wrote:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).
Click to expand...
Here's one suspect:

assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;
Click to expand...
You can drive a Z for synthesis, but you can't read one.
Consider adding an output enable signal.

-- Mike Treseler
 
"Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message news:<1027j4slqdo2b24@corp.supernews.com>...
Hi Filippo,

I assume the clk signal in your code is the AVR clock. You should implement
the interface asynchronously and when you have the data in the FPGA
synchronize it to whatever clock you have there. This is an excerpt from the
ATmega162L datasheet:

"Note that the XMEM interface is asynchronous and that the waveforms in the
figures
below are related to the internal system clock. The skew between the
internal and external
clock (XTAL1) is not guaranteed (it varies between devices, temperature, and
supply
voltage). Consequently, the XMEM interface is not suited for synchronous
operation."

Regards,
-- Georgi
Click to expand...
Teacher told us not to do an asynchronous interface , 'cause it won't
work ...

maybe he's just a crazy man... but a week ago it was asynchronous and
didn't work too
 
I made a lot of changes:
- split IO_control in two modules : an io buffer (iobuf) and the
contoller (IO_Async)
- now it's totally asynchronous
- no more extra reg
- tried to split the big always in many little ones

but now it doesn't work neither with modelsim, post place & route sim
results aren't nice.
The problem seems to be somewhere between iobuf and IO_Async because
when i try to write an address in ADDR it never arrives ?
The funny thing is that both modules work fine alone..

here's the code:
------------------------------------------------------------------------------
module IO_Async(ALE,NWR,NRD,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,rst,ibuf,obuf);

input ALE;

input NWR;

input NRD;

input [7:0] MIN;

input [7:0] MAX;

input [7:0] ibuf;

output [7:0] obuf;

output [7:0] SEL;

output [7:0] TYPEFIL;

output [7:0] AMPLIF;

output [7:0] DIVFRQ;

output rst;



reg [7:0] ADDR;

reg [7:0] obuf;

reg [7:0] SEL;

reg [7:0] TYPEFIL;

reg [7:0] AMPLIF;

reg [7:0] DIVFRQ;

reg rst;



// ciclo scrittura ADDR

always @(posedge ALE)

ADDR <= ibuf;





//ciclo scrittura rst

always @(negedge NWR)

if (ADDR == 8'b0000_0000)rst <= (ibuf[0]);

else rst <= rst;





// ciclo scrittura SEL

always @(negedge NWR)

if (ADDR == 8'b0000_0001)SEL <= ibuf;

else SEL <= SEL;







// ciclo scrittura TYPEFIL

always @(negedge NWR)

if (ADDR == 8'b0000_0010)TYPEFIL <= ibuf;

else TYPEFIL <= TYPEFIL;





// ciclo scrittura AMPLIF

always @(negedge NWR)

if (ADDR == 8'b0000_0100)AMPLIF <= ibuf;

else AMPLIF <= AMPLIF;





// ciclo scrittura DIVFRQ

always @(negedge NWR)

if (ADDR == 8'b0000_1000)DIVFRQ <= ibuf;

else DIVFRQ <= DIVFRQ;





// ciclo letture

always @(negedge NRD)

if (ADDR == 8'b0000_0000)obuf <= {7'b0,rst};

else if (ADDR == 8'b0000_0001)obuf <= SEL;

else if (ADDR == 8'b0000_0010)obuf <= TYPEFIL;

else if (ADDR == 8'b0000_0100)obuf <= AMPLIF;

else if (ADDR == 8'b0000_1000)obuf <= DIVFRQ;

else if (ADDR == 8'b0001_0000)obuf <= MIN;

else if (ADDR == 8'b0010_0000)obuf <= MAX;

else obuf <= obuf;



endmodule

_______________________________________________________________________________
-------------------------------------------------------------------------------
module iobuff(da,obuf,ibuf,dir);

input dir;

inout [7:0] da;

input [7:0] obuf;

output [7:0] ibuf;



assign da = (dir) ? 8'bzzzz_zzzz : obuf;

assign ibuf = (dir) ? da : 8'bzzzz_zzzz;



endmodule

_______________________________________________________________________________
 
"filippo" <filippdavid@yahoo.com> wrote in message
news:18add487.0402071604.6589ebbe@posting.google.com...
I made a lot of changes:
- split IO_control in two modules : an io buffer (iobuf) and the
contoller (IO_Async)
- now it's totally asynchronous
- no more extra reg
- tried to split the big always in many little ones

but now it doesn't work neither with modelsim, post place & route sim
results aren't nice.
The problem seems to be somewhere between iobuf and IO_Async because
when i try to write an address in ADDR it never arrives ?
The funny thing is that both modules work fine alone..
Click to expand...
<snip>

// ciclo scrittura ADDR

always @(posedge ALE)

ADDR <= ibuf;
Click to expand...
This should be negedge instead of posedge - look at the timing diagrams. Or
you can synthesize a latch that is transparent when ALE=1.

//ciclo scrittura rst

always @(negedge NWR)

if (ADDR == 8'b0000_0000)rst <= (ibuf[0]);

else rst <= rst;
Click to expand...
All "always @(negedge NWR)" statements should use posedge instead. The data
is not valid yet on the falling edge.

--------------------------------------------------------------------------
-----
module iobuff(da,obuf,ibuf,dir);

input dir;

inout [7:0] da;

input [7:0] obuf;

output [7:0] ibuf;



assign da = (dir) ? 8'bzzzz_zzzz : obuf;

assign ibuf = (dir) ? da : 8'bzzzz_zzzz;
Click to expand...
What is dir connected to? Also, I think you don't need a tristate bus for
ibuf.

-- Georgi
 
"Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message
// ciclo scrittura ADDR

always @(posedge ALE)

ADDR <= ibuf;

This should be negedge instead of posedge - look at the timing diagrams. Or
you can synthesize a latch that is transparent when ALE=1.

//ciclo scrittura rst

always @(negedge NWR)

if (ADDR == 8'b0000_0000)rst <= (ibuf[0]);

else rst <= rst;

All "always @(negedge NWR)" statements should use posedge instead. The data
is not valid yet on the falling edge.
Click to expand...
this are the time diagrams i got:

WRITING CICLE

ALE +--+
| |
---------+ +-------------------

NWR -----------------+ +-----------
| |
+--+

DA ----\ /-----\ /------\ /-------
xxx |adress | data | xxxxxxx
----/ \-----/ \------/ \-------


-----
module iobuff(da,obuf,ibuf,dir);

input dir;

inout [7:0] da;

input [7:0] obuf;

output [7:0] ibuf;



assign da = (dir) ? 8'bzzzz_zzzz : obuf;

assign ibuf = (dir) ? da : 8'bzzzz_zzzz;


What is dir connected to? Also, I think you don't need a tristate bus for
ibuf.

-- Georgi
Click to expand...
Now it works (modelsim) i had to split the iobuff in two buffers: one
for ibuf and one for obuf.
I know it seems crazy , but just "assign ibuf= da;" didn' t work i had
to make a tristate buff to make it work .

I hope thursday it will work on the real FPGA ^_^
 
filippdavid@yahoo.com (filippo) wrote in message news:<18add487.0402071604.6589ebbe@posting.google.com>...
I made a lot of changes:
- split IO_control in two modules : an io buffer (iobuf) and the
contoller (IO_Async)

always @(negedge NRD)
if (ADDR == 8'b0000_0000)obuf <= {7'b0,rst};
else if (ADDR == 8'b0000_0001)obuf <= SEL;
else if (ADDR == 8'b0000_0010)obuf <= TYPEFIL;
else if (ADDR == 8'b0000_0100)obuf <= AMPLIF;
else if (ADDR == 8'b0000_1000)obuf <= DIVFRQ;
else if (ADDR == 8'b0001_0000)obuf <= MIN;
else if (ADDR == 8'b0010_0000)obuf <= MAX;
else obuf <= obuf;
Click to expand...
Use a case statement. Also, there's no reason for the readback mux to
be sensitive to an edge of the read enable; it can be purely
combinatorial based on the address. Of course, I assume that the
address remains valid (and therefore the data being read back remains
valid, too) so as to meet hold time requirements on the micro inputs.

--a
 
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