need coding

[Saqib Saqi]

TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA
OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM encoding Standard.
The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE

 

[Nicolas Matringe]

Le 11/05/2014 16:58, Saqib Saqi a écrit :

TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA
OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM encoding Standard.
The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE

Yes, it definitely looks like you need to start coding.

Nicolas

 

[Saqib Saqi]

On Monday, May 12, 2014 2:03:30 PM UTC+5, Adam Górski wrote:

W dniu 2014-05-11 16:58, Saqib Saqi pisze:

TITLE

Implementation of CCSDS based Telemetry Encoder on FPGA

OBJECTIVES

Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.

OUTLINE

The project will comprise of three phases.

First phase will be the know how development of CCSDS Packet TM encoding Standard.

The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.

Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.

MAJOR EQUIPMENT & SOFTWARE REQUIRED



Hardware: FPGA kit (Spartan-3 or Virtex)

Software: Xilinx ISE





Interesting project. I could join in if you can pay ....



BR



Adam

yes i can u can email me muhammadsaqib10cs52@hotmail.com

or FB account on Search type
saqi0313saqi@yahoo.com you can add me


i'm w8ing for ur resposnse

 

[Saqib Saqi]

On Monday, May 12, 2014 12:52:58 AM UTC+5, Nicolas Matringe wrote:

Le 11/05/2014 16:58, Saqib Saqi a �crit :

TITLE

Implementation of CCSDS based Telemetry Encoder on FPGA

OBJECTIVES

Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.

OUTLINE

The project will comprise of three phases.

First phase will be the know how development of CCSDS Packet TM encoding Standard.

The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.

Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.

MAJOR EQUIPMENT & SOFTWARE REQUIRED



Hardware: FPGA kit (Spartan-3 or Virtex)

Software: Xilinx ISE





Yes, it definitely looks like you need to start coding.



Nicolas

kindly help me in packet telemetry encoder ...i need to encode all the encoder or just telemetry encoder ...help me if u can

 

[Adam Górski]

W dniu 2014-05-11 16:58, Saqib Saqi pisze:

TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA
OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM encoding Standard.
The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE

Interesting project. I could join in if you can pay ....

BR

Adam

 

[Tim Wescott]

On Sun, 11 May 2014 07:58:17 -0700, Saqib Saqi wrote:

TITLE Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using
VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM
encoding Standard.
The second phase will be the implementation of all layers of standard on
FPGA using the VHDL language. Each layer will be implemented as a
separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third
phase of the project. Complete working TM Encoder will be demonstrated
on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE

University final project?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Tim Wescott]

On Mon, 12 May 2014 11:03:30 +0200, Adam GĂłrski wrote:

W dniu 2014-05-11 16:58, Saqib Saqi pisze:
TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using
VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM
encoding Standard.
The second phase will be the implementation of all layers of standard
on FPGA using the VHDL language. Each layer will be implemented as a
separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third
phase of the project. Complete working TM Encoder will be demonstrated
on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE


Interesting project. I could join in if you can pay ....

BR

Adam

If he's offering to pay you to do his senior project, consider that
you'll be helping to graduate one more incompetent manager.

Wouldn't you rather he was one department over, in sales or something?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Adam GĂłrski]

W dniu 2014-05-12 23:26, Tim Wescott pisze:

On Mon, 12 May 2014 11:03:30 +0200, Adam GĂłrski wrote:

W dniu 2014-05-11 16:58, Saqib Saqi pisze:
TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using
VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM
encoding Standard.
The second phase will be the implementation of all layers of standard
on FPGA using the VHDL language. Each layer will be implemented as a
separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third
phase of the project. Complete working TM Encoder will be demonstrated
on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE


Interesting project. I could join in if you can pay ....

BR

Adam

If he's offering to pay you to do his senior project, consider that
you'll be helping to graduate one more incompetent manager.

Wouldn't you rather he was one department over, in sales or something?

If this is any kind of school project - I'm not interested ( no way).
I'm not going to take it for 100$. My time is much more expensive.
If this is space application for serius client ( like NASA or something
) and is interesting , "beam me up Scotty".


BR

Adam

 

[HT-Lab]

On 13/05/2014 09:47, Adam GĂłrski wrote:

W dniu 2014-05-12 23:26, Tim Wescott pisze:
On Mon, 12 May 2014 11:03:30 +0200, Adam GĂłrski wrote:

W dniu 2014-05-11 16:58, Saqib Saqi pisze:
TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using
VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM
encoding Standard.
The second phase will be the implementation of all layers of standard
on FPGA using the VHDL language. Each layer will be implemented as a
separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third
phase of the project. Complete working TM Encoder will be demonstrated
on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE


Interesting project. I could join in if you can pay ....

BR

Adam

If he's offering to pay you to do his senior project, consider that
you'll be helping to graduate one more incompetent manager.

Wouldn't you rather he was one department over, in sales or something?


If this is any kind of school project - I'm not interested ( no way).
I'm not going to take it for 100$. My time is much more expensive.
If this is space application for serius client ( like NASA or something
) and is interesting , "beam me up Scotty".

I am pretty sure Nasa already has in-house CCSDS cores, for any other
smaller space company I believe they can get the ESA CCSDS VHDL design
(for free?) under a license agreement.

I also believe (but haven't checked as I no longer work in the space
industry) that you can get most CCSDS modules (turbo codecs excluded?)
from Gaisler research.

Hans
www.ht-lab.com

BR

Adam

 

[Saqib Saqi]

On Tuesday, May 13, 2014 2:26:25 PM UTC+5, HT-Lab wrote:

On 13/05/2014 09:47, Adam Górski wrote:

W dniu 2014-05-12 23:26, Tim Wescott pisze:

On Mon, 12 May 2014 11:03:30 +0200, Adam Górski wrote:



W dniu 2014-05-11 16:58, Saqib Saqi pisze:

TITLE

Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES

Design and development of CCSDS based Telemetry Encoder on FPGA using

VHDL, for satellite applications.

OUTLINE

The project will comprise of three phases.

First phase will be the know how development of CCSDS Packet TM

encoding Standard.

The second phase will be the implementation of all layers of standard

on FPGA using the VHDL language. Each layer will be implemented as a

separate module and simulation will be performed.

Finally all the modules will be integrated as a system in the third

phase of the project. Complete working TM Encoder will be demonstrated

on FPGA kit.

MAJOR EQUIPMENT & SOFTWARE REQUIRED



Hardware: FPGA kit (Spartan-3 or Virtex)

Software: Xilinx ISE





Interesting project. I could join in if you can pay ....



BR



Adam



If he's offering to pay you to do his senior project, consider that

you'll be helping to graduate one more incompetent manager.



Wouldn't you rather he was one department over, in sales or something?





If this is any kind of school project - I'm not interested ( no way).

I'm not going to take it for 100$. My time is much more expensive.

If this is space application for serius client ( like NASA or something

) and is interesting , "beam me up Scotty".



I am pretty sure Nasa already has in-house CCSDS cores, for any other

smaller space company I believe they can get the ESA CCSDS VHDL design

(for free?) under a license agreement.



I also believe (but haven't checked as I no longer work in the space

industry) that you can get most CCSDS modules (turbo codecs excluded?)

from Gaisler research.



Hans

www.ht-lab.com

BR



Adam

i'm university student and i want me to do this project

 

[Saqib Saqi]

On Tuesday, May 13, 2014 1:47:21 PM UTC+5, Adam Górski wrote:

W dniu 2014-05-12 23:26, Tim Wescott pisze:

On Mon, 12 May 2014 11:03:30 +0200, Adam Górski wrote:



W dniu 2014-05-11 16:58, Saqib Saqi pisze:

TITLE

Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES

Design and development of CCSDS based Telemetry Encoder on FPGA using

VHDL, for satellite applications.

OUTLINE

The project will comprise of three phases.

First phase will be the know how development of CCSDS Packet TM

encoding Standard.

The second phase will be the implementation of all layers of standard

on FPGA using the VHDL language. Each layer will be implemented as a

separate module and simulation will be performed.

Finally all the modules will be integrated as a system in the third

phase of the project. Complete working TM Encoder will be demonstrated

on FPGA kit.

MAJOR EQUIPMENT & SOFTWARE REQUIRED



Hardware: FPGA kit (Spartan-3 or Virtex)

Software: Xilinx ISE





Interesting project. I could join in if you can pay ....



BR



Adam



If he's offering to pay you to do his senior project, consider that

you'll be helping to graduate one more incompetent manager.



Wouldn't you rather he was one department over, in sales or something?





If this is any kind of school project - I'm not interested ( no way).

I'm not going to take it for 100$. My time is much more expensive.

If this is space application for serius client ( like NASA or something

) and is interesting , "beam me up Scotty".





BR



Adam

if u have command on this ..then i can pay ..this is my univ.level project
if u can help this is very humble kindness for this thing

 

[Adam GĂłrski]

W dniu 2014-05-13 11:26, HT-Lab pisze:

On 13/05/2014 09:47, Adam GĂłrski wrote:
W dniu 2014-05-12 23:26, Tim Wescott pisze:
On Mon, 12 May 2014 11:03:30 +0200, Adam GĂłrski wrote:

W dniu 2014-05-11 16:58, Saqib Saqi pisze:
TITLE
Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES
Design and development of CCSDS based Telemetry Encoder on FPGA using
VHDL, for satellite applications.
OUTLINE
The project will comprise of three phases.
First phase will be the know how development of CCSDS Packet TM
encoding Standard.
The second phase will be the implementation of all layers of standard
on FPGA using the VHDL language. Each layer will be implemented as a
separate module and simulation will be performed.
Finally all the modules will be integrated as a system in the third
phase of the project. Complete working TM Encoder will be demonstrated
on FPGA kit.
MAJOR EQUIPMENT & SOFTWARE REQUIRED

Hardware: FPGA kit (Spartan-3 or Virtex)
Software: Xilinx ISE


Interesting project. I could join in if you can pay ....

BR

Adam

If he's offering to pay you to do his senior project, consider that
you'll be helping to graduate one more incompetent manager.

Wouldn't you rather he was one department over, in sales or something?


If this is any kind of school project - I'm not interested ( no way).
I'm not going to take it for 100$. My time is much more expensive.
If this is space application for serius client ( like NASA or something
) and is interesting , "beam me up Scotty".

I am pretty sure Nasa already has in-house CCSDS cores, for any other
smaller space company I believe they can get the ESA CCSDS VHDL design
(for free?) under a license agreement.

I also believe (but haven't checked as I no longer work in the space
industry) that you can get most CCSDS modules (turbo codecs excluded?)
from Gaisler research.

I'm sure it is true

Adam

 

[Tim Wescott]

On Tue, 13 May 2014 08:18:51 -0700, Saqib Saqi wrote:

if u have command on this ..then i can pay ..this is my univ.level
project if u can help this is very humble kindness for this thing

But here's the thing: university projects are assigned assuming that YOU
will do the work. If you pay someone else to do the work and pass it off
as yours, then that's cheating. You won't learn how to be a productive
engineer by cheating (engineers actually have to use the knowledge they
gain at school), you'll just get a piece of paper that says you are.

When you try to get an actual job and are asked to DO the things that you
should have learned getting your degree, you'll fail. Then you'll either
get fired, or you'll get made into a manager. You won't be a good
manager -- you'll be a horrid manager. You'll be the kind of manager who
cheats his boss (which makes his employees look bad), and cheats his
employees (which makes them look bad), and generally makes life hell for
every honest person within his event horizon.

I think I'm speaking for most of us here when I say that we take a very
dim view of cheating. Even those of us who are amoral enough to not care
about the actual cheating don't want to have to work under the kind of
manager who cheats his way through school because he can't or won't do
engineering. Since engineers tend to think in the long term, that means
that we're not interested in a little bit of money today to foster a
worse work environment for the rest of your life.

Now, if you want to actually DO the work, and all you want is some help
to understand HOW to do the work (because god knows, not every professor
is created equal, and some of them couldn't teach their way out of a
paper bag), then by all means change your approach to "I've been assigned
this project, and I need help figuring out how to get it done".

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Saqib Saqi]

On Wednesday, May 14, 2014 2:50:02 PM UTC+5, Adam Górski wrote:

W dniu 2014-05-13 17:18, Saqib Saqi pisze:

On Tuesday, May 13, 2014 1:47:21 PM UTC+5, Adam Gďż 1/2 rski wrote:

W dniu 2014-05-12 23:26, Tim Wescott pisze:



On Mon, 12 May 2014 11:03:30 +0200, Adam Gďż 1/2 rski wrote:







W dniu 2014-05-11 16:58, Saqib Saqi pisze:



TITLE



Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES



Design and development of CCSDS based Telemetry Encoder on FPGA using



VHDL, for satellite applications.



OUTLINE



The project will comprise of three phases.



First phase will be the know how development of CCSDS Packet TM



encoding Standard.



The second phase will be the implementation of all layers of standard



on FPGA using the VHDL language. Each layer will be implemented as a



separate module and simulation will be performed.



Finally all the modules will be integrated as a system in the third



phase of the project. Complete working TM Encoder will be demonstrated



on FPGA kit.



MAJOR EQUIPMENT & SOFTWARE REQUIRED







Hardware: FPGA kit (Spartan-3 or Virtex)



Software: Xilinx ISE











Interesting project. I could join in if you can pay ....







BR







Adam







If he's offering to pay you to do his senior project, consider that



you'll be helping to graduate one more incompetent manager.







Wouldn't you rather he was one department over, in sales or something?











If this is any kind of school project - I'm not interested ( no way).



I'm not going to take it for 100$. My time is much more expensive.



If this is space application for serius client ( like NASA or something



) and is interesting , "beam me up Scotty".











BR







Adam



if u have command on this ..then i can pay ..this is my univ.level project

if u can help this is very humble kindness for this thing





So , sorry then. I can help you in some difficult points if you give me

right questions.

If you cannot even start with this project - it is not for you.

I completely agree with Tim. You should start with information what kind

of project is it.





BR



Adam

@Tim @Adam
then i need some help regarding my project
the help is that ....
we just encode telemetry or on the Other Hand
Packet telemetry encoder listed 8 thing ....

The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises the following:
* Telemetry Encoder (TME)
* Reed-Solomon Encoder (RSE)
* Turbo Encoder (TE)
* Pseudo-Randomiser (PSR)
* Non-Return-to-Zero Mark encoder (NRZ)
* Convolutional Encoder (CE)
* Split-Phase Level modulator (SP)
* Clock Divider (CD)
we encode just Telemetry encoder or
all of the other encoder
i'm confuse

 

[Adam Górski]

W dniu 2014-05-13 17:18, Saqib Saqi pisze:

On Tuesday, May 13, 2014 1:47:21 PM UTC+5, Adam Górski wrote:
W dniu 2014-05-12 23:26, Tim Wescott pisze:

On Mon, 12 May 2014 11:03:30 +0200, Adam Górski wrote:



W dniu 2014-05-11 16:58, Saqib Saqi pisze:

TITLE

Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES

Design and development of CCSDS based Telemetry Encoder on FPGA using

VHDL, for satellite applications.

OUTLINE

The project will comprise of three phases.

First phase will be the know how development of CCSDS Packet TM

encoding Standard.

The second phase will be the implementation of all layers of standard

on FPGA using the VHDL language. Each layer will be implemented as a

separate module and simulation will be performed.

Finally all the modules will be integrated as a system in the third

phase of the project. Complete working TM Encoder will be demonstrated

on FPGA kit.

MAJOR EQUIPMENT & SOFTWARE REQUIRED



Hardware: FPGA kit (Spartan-3 or Virtex)

Software: Xilinx ISE





Interesting project. I could join in if you can pay ....



BR



Adam



If he's offering to pay you to do his senior project, consider that

you'll be helping to graduate one more incompetent manager.



Wouldn't you rather he was one department over, in sales or something?





If this is any kind of school project - I'm not interested ( no way).

I'm not going to take it for 100$. My time is much more expensive.

If this is space application for serius client ( like NASA or something

) and is interesting , "beam me up Scotty".





BR



Adam

if u have command on this ..then i can pay ..this is my univ.level project
if u can help this is very humble kindness for this thing

So , sorry then. I can help you in some difficult points if you give me
right questions.
If you cannot even start with this project - it is not for you.
I completely agree with Tim. You should start with information what kind
of project is it.


BR

Adam

 

[Tom Gardner]

On 14/05/14 14:37, Saqib Saqi wrote:

we encode just Telemetry encoder or
all of the other encoder
i'm confuse

Only your teacher can resolve that confusion. Ask him
what he expects you to complete in order that he will
give you full marks.

 

[Tim Wescott]

On Wed, 14 May 2014 06:37:19 -0700, Saqib Saqi wrote:

ethics discussion snipped

@Tim @Adam then i need some help regarding my project the help is that
....
we just encode telemetry or on the Other Hand Packet telemetry encoder
listed 8 thing ....

The Packet Telemetry Encoder (PTME) VHDL model comprises several
encoders and modulators implementing the Consultative Committee for
Space Data Systems (CCSDS) recommendations and the European Space Agency
(ESA) Procedures, Standards and Specifications (PSS) for telemetry and
channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises
the following:
* Telemetry Encoder (TME)
* Reed-Solomon Encoder (RSE)
* Turbo Encoder (TE)
* Pseudo-Randomiser (PSR)
* Non-Return-to-Zero Mark encoder (NRZ)
* Convolutional Encoder (CE)
* Split-Phase Level modulator (SP)
* Clock Divider (CD)
we encode just Telemetry encoder or all of the other encoder i'm confuse

Like Tom said, you need to ask your prof. This is a pretty good
simulation of engineering in the real world: your boss, or a customer, or
Sales, or whoever, will ask you to do something in general terms that
turn out to be ambiguous. You need to deliver something very specific,
so it's your job to take that English-language (or whatever language) and
translate it into Engineering-English.

You want to do this BEFORE you've spent much time on actual design --
because any time spent designing the wrong thing is just time wasted.

The whole list of things there would be a pretty daunting task for one
student to undertake as a project. It's not totally undoable, but I
would hope that your prof is thinking more along the lines of having you
build a piece of it, either to go onto something that someone else has
done, or to serve as a foundation for someone else's work.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Saqib Saqi]

On Thursday, May 15, 2014 2:41:43 PM UTC+5, Adam Górski wrote:

@Tim @Adam

then i need some help regarding my project

the help is that ....

we just encode telemetry or on the Other Hand

Packet telemetry encoder listed 8 thing ....



The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises the following:

* Telemetry Encoder (TME)

* Reed-Solomon Encoder (RSE)

* Turbo Encoder (TE)

* Pseudo-Randomiser (PSR)

* Non-Return-to-Zero Mark encoder (NRZ)

* Convolutional Encoder (CE)

* Split-Phase Level modulator (SP)

* Clock Divider (CD)

we encode just Telemetry encoder or

all of the other encoder

i'm confuse





Do you expect from me ( us ) answer to this question ?

In my opinion it is lot of work if you going to implement all of them.

Only RSE is big enough for you I think.



Adam

@adam @tim
you both are right ,,but something really interesting fact that you don't know .
the fact is that my Supervisor is not command from these kinds of topic....

so after your some solid reason ...
here just one question is asked to u ...
the question is..................
implement only one telemetry encoder


7OSI model layer i think only implement on telemetry encoder
and other encoder don't use 7OSI layer model because
The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.

what can you suggest for me ???Please just Technical help for both of you

 

[Adam Górski]

@Tim @Adam
then i need some help regarding my project
the help is that ....
we just encode telemetry or on the Other Hand
Packet telemetry encoder listed 8 thing ....

The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises the following:
* Telemetry Encoder (TME)
* Reed-Solomon Encoder (RSE)
* Turbo Encoder (TE)
* Pseudo-Randomiser (PSR)
* Non-Return-to-Zero Mark encoder (NRZ)
* Convolutional Encoder (CE)
* Split-Phase Level modulator (SP)
* Clock Divider (CD)
we encode just Telemetry encoder or
all of the other encoder
i'm confuse

Do you expect from me ( us ) answer to this question ?
In my opinion it is lot of work if you going to implement all of them.
Only RSE is big enough for you I think.

Adam

 

[Nikolaos Kavvadias]

Dear Saqib,

> > > then i need some help regarding my project

Hans (Tiggeler) has gave you an excellent overview of what exactly is available regarding CCSDS Telemetry Encoder IP.

I am interested in helping you (I provide paid support).

So if this is an academic exercise, and plagiarism is not tolerated then someone has to start from the specs (either directly you or the contractee).

Do you have a deadline and budget to see if this is feasible?


Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

the help is that ....



we just encode telemetry or on the Other Hand



Packet telemetry encoder listed 8 thing ....







The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises the following:



* Telemetry Encoder (TME)



* Reed-Solomon Encoder (RSE)



* Turbo Encoder (TE)



* Pseudo-Randomiser (PSR)



* Non-Return-to-Zero Mark encoder (NRZ)



* Convolutional Encoder (CE)



* Split-Phase Level modulator (SP)



* Clock Divider (CD)



we encode just Telemetry encoder or



all of the other encoder



i'm confuse











Do you expect from me ( us ) answer to this question ?



In my opinion it is lot of work if you going to implement all of them.



Only RSE is big enough for you I think.







Adam







@adam @tim

you both are right ,,but something really interesting fact that you don't know .

the fact is that my Supervisor is not command from these kinds of topic.....



so after your some solid reason ...

here just one question is asked to u ...

the question is..................

implement only one telemetry encoder





7OSI model layer i think only implement on telemetry encoder

and other encoder don't use 7OSI layer model because

The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.



what can you suggest for me ???Please just Technical help for both of you