Need an algorithm for BIST to test stuck at faults in an FPG

[pavan.bvsrc@gmail.com]

Hi,

I need an algorithm or verilog/vhdl code for Built in self test that
can detect stuck at faults in an FPGA. Please help me in this case

Thanks,
Pavan

 

[Martin Thompson]

"pavan.bvsrc@gmail.com" <pavan.bvsrc@gmail.com> writes:

Hi,

I need an algorithm or verilog/vhdl code for Built in self test that
can detect stuck at faults in an FPGA. Please help me in this case

Why? FPGAs are already tested when you get them.

You could ask on comp.arch.fpga, but they'll say much the same I
imagine

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

 

FPGAs offer JTAG and boundary scan which you can use to access
internals for design verification purposes (testing the design).
Manufacturing testing of FPGAs (like stuck-at testing) is already
performed on FPGAs when you buy them.

Maybe you need to implement a BIST variant in an FPGA just to
explore/practice, then google LFSR BIST VERILOG.

Good Luck.

HrH