Need AD9501 replacement

[Joerg]

Jon Elson wrote:

Joerg wrote:


Well, then you are almost home with that project. The absolute timing
will be a challenge unless you can calibrate and get all the tempcos out.


Oh, not really home yet. Simulation just says I don't need to break any
physical laws to get what I want, it doesn't prove I'll get the
performance with real-world parts and a PCB layout. I've got parts on
order, and then I'll find out. We don't worry too much about temp
coeff. as this gear is run in a lab environment with forced air cooling
designed for a boatload of ECL chips. And, we do calibrate the thing,
and have individual cal constants for each channel.

Thanks for your comments!

You are welcome. Probably you'll need the best RF film caps you can get
for the ramp circuits.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Jon Elson]

Joerg wrote:

Well, then you are almost home with that project. The absolute timing
will be a challenge unless you can calibrate and get all the tempcos out.

Oh, not really home yet. Simulation just says I don't need to break any
physical laws to get what I want, it doesn't prove I'll get the
performance with real-world parts and a PCB layout. I've got parts on
order, and then I'll find out. We don't worry too much about temp
coeff. as this gear is run in a lab environment with forced air cooling
designed for a boatload of ECL chips. And, we do calibrate the thing,
and have individual cal constants for each channel.

Thanks for your comments!

Jon

 

[Joerg]

Jon Elson wrote:

Joerg wrote:
Jon Elson wrote:
We need a reset MOSFET with
low capacitance.


Take a look at the 2N7002. No idea if a similar one comes in SC75
though, for extra space saving. Open drain CMOS gates/inverters might
be another option.

Capacitor tolerance and drift could become a challenge. Then again a
world without such challenges wouldn't need engineers ;-)

Much too much capacitance. The BSS123 is less than half as much. I am
ordering some for a prototype. The comonents are actually smaller with
a first-cut layout than the AD9501JP, 20 pin PLCC.

Yep, sorry, that's the one I meant. The BSS123 is my favorite jelly-bean
FET. For really low C you might want to look at JFETs.

Did the AD9501 really do 20psec? It's possible but tough. I am usually
not a friend of FPGA but this would be one application where I'd
consider them, because of the huge number of channels.

It did 20 ps RESOLUTION, I have no idea what the actual jitter or
stability was in that range, don't have the gear to measure that without
intense effort, but it was good enough for our needs. Really, even 250
ps steps probably would have been good enough, but we wanted the minimum
delay setting down at 15 ns or so, and we needed max integrator current
and as close to zero external capacitance to get to there.

Another option might be a method similar to a tuning fork. A resonant
ciruit is "pinged" by the nuclear detector pulse and then a zero
crosser begins counting, plus adding a vernier delay at the end. But
this is even more esoteric, will require more study and might end up
not being too practical.


None of this is practical when I need it to take 1/3 In. sq. and cost no
more than $10 - 15 a channel, with 64 of them on a board. I basically
mocked up the workings of the AD9501, so a current source, a capacitor,
a comparator, a DAC to set the comparator threshold, and a FF to reset
the integrator when finished. I guess I have the cost down to about $5
a channel, smaller than the PLCC-20 package, and all new components that
I can get for a while into the future. Simulation says it will
outperform the 9501, but I'll be happy if I can just equal that
performance.

Well, then you are almost home with that project. The absolute timing
will be a challenge unless you can calibrate and get all the tempcos out.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Jon Elson]

Joerg wrote:

Jon Elson wrote:
We need a reset MOSFET with
low capacitance.


Take a look at the 2N7002. No idea if a similar one comes in SC75
though, for extra space saving. Open drain CMOS gates/inverters might be
another option.

Capacitor tolerance and drift could become a challenge. Then again a
world without such challenges wouldn't need engineers ;-)

Much too much capacitance. The BSS123 is less than half as much. I am

ordering some for a prototype. The comonents are actually smaller with
a first-cut layout than the AD9501JP, 20 pin PLCC.

Did the AD9501 really do 20psec? It's possible but tough. I am usually
not a friend of FPGA but this would be one application where I'd
consider them, because of the huge number of channels.

It did 20 ps RESOLUTION, I have no idea what the actual jitter or

stability was in that range, don't have the gear to measure that without
intense effort, but it was good enough for our needs. Really, even 250
ps steps probably would have been good enough, but we wanted the minimum
delay setting down at 15 ns or so, and we needed max integrator current
and as close to zero external capacitance to get to there.

Another option might be a method similar to a tuning fork. A resonant
ciruit is "pinged" by the nuclear detector pulse and then a zero crosser
begins counting, plus adding a vernier delay at the end. But this is
even more esoteric, will require more study and might end up not being
too practical.

None of this is practical when I need it to take 1/3 In. sq. and cost no
more than $10 - 15 a channel, with 64 of them on a board. I basically
mocked up the workings of the AD9501, so a current source, a capacitor,
a comparator, a DAC to set the comparator threshold, and a FF to reset
the integrator when finished. I guess I have the cost down to about $5
a channel, smaller than the PLCC-20 package, and all new components that
I can get for a while into the future. Simulation says it will
outperform the 9501, but I'll be happy if I can just equal that performance.

Jon

 

[Jon Elson]

Hello,

I have been using the Analog Devices AD9501 programmable delay chip in
some gear, and was planning on designing a new board with them when I
discovered they were obsolete, and becoming scarce. The chip is just
about ideal for what we are doing, and I've found nothing that comes close.

We use it to form a wide-range programmable one-shot, by using a CMOS
switch to switch in resistors and caps, obtaining 5 overlapping ranges
of time delay, from 0-50 ns to 0-15 us. It has an 8-bit DAC to set the
exact delay within the range. We can't use clocked, digital techniques
because the input is from nuclear detectors, the particle arrival time
is totally non-deterministic, and we need a jitter down under a ns on
the short ranges.

Does anyone know of a compact device that does as much of this as
possible in one chip? I can build the same general function out of a
bunch of parts (8 channel DAC, current source, comparator, flip-flop)
but it will be hard to pack it in the same area even using chip-scale
parts. On this board we want to put 64 of these functions on a 7x9" area.

Thanks for any tips or ideas!

Jon

 

[Jon Elson]

Joerg wrote:

Jon Elson wrote:

Hello,

I have been using the Analog Devices AD9501 programmable delay chip in
some gear, and was planning on designing a new board with them when I
discovered they were obsolete, and becoming scarce. The chip is just
about ideal for what we are doing, and I've found nothing that comes
close.

We use it to form a wide-range programmable one-shot, by using a CMOS
switch to switch in resistors and caps, obtaining 5 overlapping ranges
of time delay, from 0-50 ns to 0-15 us. It has an 8-bit DAC to set
the exact delay within the range. We can't use clocked, digital
techniques because the input is from nuclear detectors, the particle
arrival time is totally non-deterministic, and we need a jitter down
under a ns on the short ranges.

Does anyone know of a compact device that does as much of this as
possible in one chip? I can build the same general function out of a
bunch of parts (8 channel DAC, current source, comparator, flip-flop)
but it will be hard to pack it in the same area even using chip-scale
parts. On this board we want to put 64 of these functions on a 7x9"
area.

Thanks for any tips or ideas!


No idea if they have anything suitable but might be worth a call:

http://www.datadelay.com/asp/prog.asp

They have a wide range of parts, but each one has a certain range and
step size. If I could figure out how to get 64 socketed ICs onto the
board, that is a possible solution. But, the scheme I have worked out
for the AD9501 with range switching allows you to set the timing range
under computer control, and then use the DAC feature of the chip to set
the time delay within the range. So, you can immediately go from 0-50
ns in 25 ps steps to 0-15 us in 50 ns steps.

Anyhow, I might be partially to blame for the demise of programmable
delay chips because I kicked them out of existing designs left and
right. Went with inductors and variable resistors, FET or PIN diodes,
whatever was decently priced and available. Usually servoed. 1nsec
jitter would have been totally intolerable in my cases, had to be in the
tens of psec. No way to expand the available real estate a bit?

Well, since the signals are not repetitive, we can't do any servo
techniques. We may not see a signal for 5 seconds at a time. Real
estate is flexible, but we have a module that fits into a card cage, and
it would be a great fit to get 64 of these on one board.

Jon

 

[Joerg]

Jon Elson wrote:

Hello,

I have been using the Analog Devices AD9501 programmable delay chip in
some gear, and was planning on designing a new board with them when I
discovered they were obsolete, and becoming scarce. The chip is just
about ideal for what we are doing, and I've found nothing that comes close.

We use it to form a wide-range programmable one-shot, by using a CMOS
switch to switch in resistors and caps, obtaining 5 overlapping ranges
of time delay, from 0-50 ns to 0-15 us. It has an 8-bit DAC to set the
exact delay within the range. We can't use clocked, digital techniques
because the input is from nuclear detectors, the particle arrival time
is totally non-deterministic, and we need a jitter down under a ns on
the short ranges.

Does anyone know of a compact device that does as much of this as
possible in one chip? I can build the same general function out of a
bunch of parts (8 channel DAC, current source, comparator, flip-flop)
but it will be hard to pack it in the same area even using chip-scale
parts. On this board we want to put 64 of these functions on a 7x9" area.

Thanks for any tips or ideas!

No idea if they have anything suitable but might be worth a call:

http://www.datadelay.com/asp/prog.asp

Anyhow, I might be partially to blame for the demise of programmable
delay chips because I kicked them out of existing designs left and
right. Went with inductors and variable resistors, FET or PIN diodes,
whatever was decently priced and available. Usually servoed. 1nsec
jitter would have been totally intolerable in my cases, had to be in the
tens of psec. No way to expand the available real estate a bit?

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Joerg]

Jon Elson wrote:

Joerg wrote:
Jon Elson wrote:

Hello,

I have been using the Analog Devices AD9501 programmable delay chip
in some gear, and was planning on designing a new board with them
when I discovered they were obsolete, and becoming scarce. The chip
is just
about ideal for what we are doing, and I've found nothing that comes
close.

We use it to form a wide-range programmable one-shot, by using a CMOS
switch to switch in resistors and caps, obtaining 5 overlapping
ranges of time delay, from 0-50 ns to 0-15 us. It has an 8-bit DAC
to set the exact delay within the range. We can't use clocked,
digital techniques because the input is from nuclear detectors, the
particle arrival time is totally non-deterministic, and we need a
jitter down under a ns on the short ranges.

Does anyone know of a compact device that does as much of this as
possible in one chip? I can build the same general function out of a
bunch of parts (8 channel DAC, current source, comparator, flip-flop)
but it will be hard to pack it in the same area even using chip-scale
parts. On this board we want to put 64 of these functions on a 7x9"
area.

Thanks for any tips or ideas!


No idea if they have anything suitable but might be worth a call:

http://www.datadelay.com/asp/prog.asp

They have a wide range of parts, but each one has a certain range and
step size. If I could figure out how to get 64 socketed ICs onto the
board, that is a possible solution. But, the scheme I have worked out
for the AD9501 with range switching allows you to set the timing range
under computer control, and then use the DAC feature of the chip to set
the time delay within the range. So, you can immediately go from 0-50
ns in 25 ps steps to 0-15 us in 50 ns steps.

No need for 64. You can stagger different ones in "R2R" fashion. If the
precision holds, that is.

Anyhow, I might be partially to blame for the demise of programmable
delay chips because I kicked them out of existing designs left and
right. Went with inductors and variable resistors, FET or PIN diodes,
whatever was decently priced and available. Usually servoed. 1nsec
jitter would have been totally intolerable in my cases, had to be in
the tens of psec. No way to expand the available real estate a bit?


Well, since the signals are not repetitive, we can't do any servo
techniques. We may not see a signal for 5 seconds at a time. Real
estate is flexible, but we have a module that fits into a card cage, and
it would be a great fit to get 64 of these on one board.

I didn't always servo on the signal (sometimes I did though). I servoed
the path resistance of the FET or PIN diode by using a 2nd one on the
same die. That 2ns FET or PIN was in a closed loop so I could
essentially set a rather precise path resistance on the one that was in
the RF path.

Servo on the signal in my cases went like this: CMOS mux up front,
switch to cal signal, servo the delay, then switch back to the signal
you want to delay. This was repeated at convenient intervals, often a
frame reset or whatever the system guys gave me. With this "test signal
servo" method I could use rather mundane and thus cheap parts, no need
for any duals.

If you cannot tolerate any interruptions you could just build the 2nd
scenario twice. While channel A servoes channel B processes your signal,
then they switch places, and so on. This can be pretty slow because FETs
and PIN diodes don't drift too fast unless a Siberian blizzard smashes
the window and blows in ;-)

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Jon Elson]

Joerg wrote:

No need for 64. You can stagger different ones in "R2R" fashion. If the
precision holds, that is.

I have need to process 64 totally independant signal channels, that's

why I wanted to put 64 of them on one board. I needed only ONE AD9501
to get the wide range of timings required. Putting several of the Data
Delay or Rhombus programmable delay chips still won't get me ANYWHERE
NEAR to 15 us maximum time delay.

Servo on the signal in my cases went like this: CMOS mux up front,
switch to cal signal, servo the delay, then switch back to the signal
you want to delay. This was repeated at convenient intervals, often a
frame reset or whatever the system guys gave me. With this "test signal
servo" method I could use rather mundane and thus cheap parts, no need
for any duals.

I can't switch away from the real signal, ever, as I might lose the one

event of interest all week! (That's a slight exxageration, but we
really can't have 64 auto-calibration systems going on here. The AD9501
was just perfect for this job, and was free enough of drift that we only
did an overall calibration once.)

Jon

 

[Joerg]

Jon Elson wrote:

Joerg wrote:
No need for 64. You can stagger different ones in "R2R" fashion. If
the precision holds, that is.

I have need to process 64 totally independant signal channels, that's
why I wanted to put 64 of them on one board. I needed only ONE AD9501
to get the wide range of timings required. Putting several of the Data
Delay or Rhombus programmable delay chips still won't get me ANYWHERE
NEAR to 15 us maximum time delay.

Servo on the signal in my cases went like this: CMOS mux up front,
switch to cal signal, servo the delay, then switch back to the signal
you want to delay. This was repeated at convenient intervals, often a
frame reset or whatever the system guys gave me. With this "test
signal servo" method I could use rather mundane and thus cheap parts,
no need for any duals.

I can't switch away from the real signal, ever, as I might lose the one
event of interest all week! (That's a slight exxageration, but we
really can't have 64 auto-calibration systems going on here. The AD9501
was just perfect for this job, and was free enough of drift that we only
did an overall calibration once.)

If Rochester or other places don't have any AD9501 left you may be out
of luck here. There just isn't a market for this stuff.

Of course, you could build a precision ramp generator yourself but
you'll need a DAC, comparator and all that and it's going to be larger.
The good news is that there are plenty of good 8-ch DACs and comparators
usually come in 4-packs, all available in tiny TSSOP packages. If this
is a product you have to manufacture for years to come you almost have
no other choice because any integrated solution would be a boutique part
that can vanish any time.

In ultrasound we use more esoteric timing schemes where precision is
paramount. Not sure if something like this would work in your
application but may be worth a thought:

Your delay gen runs on a fixed clock and a programmable register sets
the number of delay "bins". Pretty much every uC can do that, some
possibly up to 100MHz. Now your nuclear detector trigger signal happens
to arrive not on a clock transition but, say, 4nsec later. Every clock
cycle you start an RC ramp that gets reset by the next clock cycle but
the event of a trigger stops that and the cap holds its value. This is
fed into IN- of a fast comparator. At the output of your timing chain
(where the coarsely delayed signal comes out) you have the same RC ramp
going, also with the same discharge upon clock edge. The IN+ comparator
input is connected to that output RC. Therefore, the comparator will
switch when that output RC has reached the same value as the input RC.
Now your output would be delayed by the same 4nsec, making the whole
thing synchronous to your trigger again. Afterwards the first RC resumes
its charge/discharge scenario, looking out for the next trigger. The RC
ramp does not have to be too linear because the RC at the output would
have the same charge characteristic.

You might need a little glue logic to polish all this but it shouldn't
be too space consuming. Possibly you can use timers in micro controllers
as the heart of it and then you get nice RS485, SPI, I2C or whatever bus
architectures almost for free, usually even selectable and with comfy
example code in header files.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Jon Elson]

Joerg wrote:

Jon Elson wrote:
If Rochester or other places don't have any AD9501 left you may be out
of luck here. There just isn't a market for this stuff.

Of course, you could build a precision ramp generator yourself but
you'll need a DAC, comparator and all that and it's going to be larger.
The good news is that there are plenty of good 8-ch DACs and comparators
usually come in 4-packs, all available in tiny TSSOP packages. If this
is a product you have to manufacture for years to come you almost have
no other choice because any integrated solution would be a boutique part
that can vanish any time.

Yup, that's what I'm looking at now. We have a chip scale packaged

comparator, the ADCMP603, 3 mm square. A good DAC is the LTC1660, the
FF could be a 74LVC1G175 in an SOT-23 sized package. The circuit we had
with the AD9501 could get down to about 15 ns as the minimum delay. I
have serious doubts we can go that low with a pile of discrete parts,
but I will look at it. We need a reset MOSFET with low capacitance.

In ultrasound we use more esoteric timing schemes where precision is
paramount. Not sure if something like this would work in your
application but may be worth a thought:

Your delay gen runs on a fixed clock and a programmable register sets
the number of delay "bins". Pretty much every uC can do that, some
possibly up to 100MHz. Now your nuclear detector trigger signal happens
to arrive not on a clock transition but, say, 4nsec later. <snip

I just don't see how to implement 64 delays like this with resolution
down to 20 ps and max delays up to 15 us. I'm sure I could do a few
channels the way you suggest, but the amount of multiplexing, etc. just
seems like it can't be done that way.

Jon

 

[Joerg]

Jon Elson wrote:

Joerg wrote:
Jon Elson wrote:
If Rochester or other places don't have any AD9501 left you may be out
of luck here. There just isn't a market for this stuff.

Of course, you could build a precision ramp generator yourself but
you'll need a DAC, comparator and all that and it's going to be
larger. The good news is that there are plenty of good 8-ch DACs and
comparators usually come in 4-packs, all available in tiny TSSOP
packages. If this is a product you have to manufacture for years to
come you almost have no other choice because any integrated solution
would be a boutique part that can vanish any time.

Yup, that's what I'm looking at now. We have a chip scale packaged
comparator, the ADCMP603, 3 mm square. A good DAC is the LTC1660, the
FF could be a 74LVC1G175 in an SOT-23 sized package. The circuit we had
with the AD9501 could get down to about 15 ns as the minimum delay. I
have serious doubts we can go that low with a pile of discrete parts,
but I will look at it. We need a reset MOSFET with low capacitance.

Take a look at the 2N7002. No idea if a similar one comes in SC75
though, for extra space saving. Open drain CMOS gates/inverters might be
another option.

Capacitor tolerance and drift could become a challenge. Then again a
world without such challenges wouldn't need engineers ;-)

In ultrasound we use more esoteric timing schemes where precision is
paramount. Not sure if something like this would work in your
application but may be worth a thought:

Your delay gen runs on a fixed clock and a programmable register sets
the number of delay "bins". Pretty much every uC can do that, some
possibly up to 100MHz. Now your nuclear detector trigger signal
happens to arrive not on a clock transition but, say, 4nsec later.
snip

I just don't see how to implement 64 delays like this with resolution
down to 20 ps and max delays up to 15 us. I'm sure I could do a few
channels the way you suggest, but the amount of multiplexing, etc. just
seems like it can't be done that way.

Did the AD9501 really do 20psec? It's possible but tough. I am usually
not a friend of FPGA but this would be one application where I'd
consider them, because of the huge number of channels.

Another option might be a method similar to a tuning fork. A resonant
ciruit is "pinged" by the nuclear detector pulse and then a zero crosser
begins counting, plus adding a vernier delay at the end. But this is
even more esoteric, will require more study and might end up not being
too practical.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[kilowatt]

Hello Jon

I am aware that the AD9501 are plentiful in the surplus inventory
market.

America II has 117 pcs in their stock. Panamerica electronics has
2000
or more. All with date codes 00 to 02. phone number is 514-257-1324.

My inventory has a total of 12,000 line items and 2 million parts in
total. But
no AD9501's If you need anything in the older vintage era keep me in
mind.

cheers
KW

******************
On Oct 31, 12:00 pm, Joerg <notthisjoerg...@removethispacbell.net>
wrote:

Jon Elson wrote:
Hello,

I have been using the Analog Devices AD9501 programmable delay chip in
some gear, and was planning on designing a new board with them when I
discovered they were obsolete, and becoming scarce. The chip is just
about ideal for what we are doing, and I've found nothing that comes close.

We use it to form a wide-range programmable one-shot, by using a CMOS
switch to switch in resistors and caps, obtaining 5 overlapping ranges
of time delay, from 0-50 ns to 0-15 us. It has an 8-bit DAC to set the
exact delay within the range. We can't use clocked, digital techniques
because the input is from nuclear detectors, the particle arrival time
is totally non-deterministic, and we need a jitter down under a ns on
the short ranges.

Does anyone know of a compact device that does as much of this as
possible in one chip? I can build the same general function out of a
bunch of parts (8 channel DAC, current source, comparator, flip-flop)
but it will be hard to pack it in the same area even using chip-scale
parts. On this board we want to put 64 of these functions on a 7x9" area.

Thanks for any tips or ideas!

No idea if they have anything suitable but might be worth a call:

http://www.datadelay.com/asp/prog.asp

Anyhow, I might be partially to blame for the demise of programmable
delay chips because I kicked them out of existing designs left and
right. Went with inductors and variable resistors, FET or PIN diodes,
whatever was decently priced and available. Usually servoed. 1nsec
jitter would have been totally intolerable in my cases, had to be in the
tens of psec. No way to expand the available real estate a bit?

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Joseph H Allen]

The AD9501 was a cool chip, it sucks that it's gone. I almost used it for
an equivalent time sampling trigger.

Do a google search for "timing vernier" chips. I found this one:
http://www.micrel.com/_PDF/HBW/sy605.pdf, but it's max delay is 40 ns.
Maybe they have another with longer delay, or use this in series with a
programmable delay line from Data Delay Devices.

So, do you really need to delay signals (perhaps to synchronize them) or are
you trying to measure when an edge occurs?

Here's a crazy idea: use etch delay for a multi-tap delay line. Capture all
taps with flip flops synchronized with a low jitter crystal oscillator. The
cycle number and the tap number gives the measured delay. Maybe you can get
16 taps and run at 500 MHz for 125 ps resolution. Maybe use the I/O pads of
an FPGA for the flops, but FPGA jitter is usually not good.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}