Need a few tips working with an Xilinx FPGA

F

Fred H

Guest
I'm pretty new to FPGA-programming, and I've yet to understand
quite of the steps I go through from compiling my vhdl-files,
to finally generating bit-files.

I'm working with a Xilinx II Pro FPGA, using ISE 6.1i, and I'm
only starting to get familiar with the tools. But I'm having
some problems understanding what all the (automated) steps do,
and what they actually mean.

What I want to know, is the following:

1. What does the "Translate" step do? What is actually produced
by this step in the implementation ladder?
2. What happens in the "Map" stage, and what is produced?
3. What is left for "Place & Route" to do? (A whole lot I
suppose, since it takes so long...)

Well, you get the picture. I'm a genuine newbie, and I want to
know what the he... is going on when I skillfully double click
the "Implement Design" icon :p

Any commens, or links to introductory guides will be greatly
appreaciated. And I might as well warn you right away. I will
probably bother you guys with questions about whe myriad of
different files produced during the "implement design" process
when I'm starting to undersand what is actually happening during
that process.

Sincerely
-Fred, Norway.
 
And I might as well warn you right away. I will
probably bother you guys with questions about whe myriad of
different files produced during the "implement design" process
when I'm starting to undersand what is actually happening during
that process.
Click to expand...
Actually, I'll start right away:

- Which process(es) create the ucf and pcf files?
- Which process(es) use the ucf and pcf files?
- Which process(es) will overwrite my manually
created ucf and pcf files, and what can I do
about it?
 
Hello Fred,

reading the sites that you find at
http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm
makes you probably forget your questions :0)

Christian
 
Pĺ Thu, 04 Dec 2003 13:23:55 +0100, skrev Christian Haase
<nospams@today.de>:

Hello Fred,

reading the sites that you find at
http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm
makes you probably forget your questions :0)

Christian
Click to expand...
Just what I was looking for. Thanks a lot :)
 
Hi,

You can find some answers to your questions here:

http://www.engr.sjsu.edu/~crabill/lab5.pdf

Eric

Fred H wrote:
I'm pretty new to FPGA-programming, and I've yet to understand
quite of the steps I go through from compiling my vhdl-files,
to finally generating bit-files.

I'm working with a Xilinx II Pro FPGA, using ISE 6.1i, and I'm
only starting to get familiar with the tools. But I'm having
some problems understanding what all the (automated) steps do,
and what they actually mean.

What I want to know, is the following:

1. What does the "Translate" step do? What is actually produced
by this step in the implementation ladder?
2. What happens in the "Map" stage, and what is produced?
3. What is left for "Place & Route" to do? (A whole lot I
suppose, since it takes so long...)

Well, you get the picture. I'm a genuine newbie, and I want to
know what the he... is going on when I skillfully double click
the "Implement Design" icon :p

Any commens, or links to introductory guides will be greatly
appreaciated. And I might as well warn you right away. I will
probably bother you guys with questions about whe myriad of
different files produced during the "implement design" process
when I'm starting to undersand what is actually happening during
that process.

Sincerely
-Fred, Norway.
Click to expand...
 
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