NDL to VERILOG TRANSLATION ?

Hello,
I have to convert an old LSI ASIC to other up to date process.
The LSI library is lcb500K and gate level is NDL format.
Could some body know a tool or any way to convert this NDL format to
verilog format. Could some body provide me or give me place where I
could download this lcb500K library for synopys tool or leonardo.
Or may be somebody have a good experience in maner to do such
convertion.

Thanks by advance
Jean-Eric LEROY
Ps: You could reply directly to my e-mail address
jean-eric.leroy@barco.com

 

[Petter Gustad]

jean-eric.leroy@barco.com writes:

I have to convert an old LSI ASIC to other up to date process.
The LSI library is lcb500K and gate level is NDL format.
Could some body know a tool or any way to convert this NDL format to

There is a program in the LSI toolkit called "lsinetlist" where you
can specify -language ndl and -destination verilog to get your netlist
converted.

verilog format. Could some body provide me or give me place where I
could download this lcb500K library for synopys tool or leonardo.

You have to get the toolkit/flexstream library from LSI logic.

What was the format of the RTL/netlist in the first place? The most
common way is to go from Verilog(or VHDL) to EDIF, then go from EDIF
to NDL.

Petter
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Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<87ptihy57b.fsf@filestore.home.gustad.com>...

jean-eric.leroy@barco.com writes:

I have to convert an old LSI ASIC to other up to date process.
The LSI library is lcb500K and gate level is NDL format.
Could some body know a tool or any way to convert this NDL format to

There is a program in the LSI toolkit called "lsinetlist" where you
can specify -language ndl and -destination verilog to get your netlist
converted.

verilog format. Could some body provide me or give me place where I
could download this lcb500K library for synopys tool or leonardo.

You have to get the toolkit/flexstream library from LSI logic.

What was the format of the RTL/netlist in the first place? The most
common way is to go from Verilog(or VHDL) to EDIF, then go from EDIF
to NDL.
The problem is I just have database of this circuit sent to foundry,

therefore I haven’t any RTL net list or any other LSI tools. My
goal is to convert this gate level net list toward verilog gate level
net list, after that with a good data book of this library I could
unmap this gate level net toward an other library.
The translation from ndl to verilog seems to be OK throughout Synopsys
tool, therefore now I’m looking for the lcb500k data book,
it’s quite impossible to find it.
In any case I thank you to have time to answer me.
Best regards
Jean-Eric

Petter