ncvhdl problem

[Metin Yerlikaya]

Hi,

i have the following problem & appreciate any hints on this.

i used ncverilog all the time before. There, it was possible to use
system tasks($recordvar) within the testbench to write out *trn & *dsn
files which you one can use later with signalscan for debugging signal
waveforms.

Now i have to use vhdl and ncvhdl. Is it true that above method is not
possible for vhdl testbenchs.
How can i generate *trn *dsn. files with vhdl. Whats the most straight
and sophisticated way to do this. I don't want to use nclaunch nor
interactive ncsim tcl shell. I want to run the ncsim and later if
needed check the waveforms.

Another question:

would it work if i write a verilog testbench and instantiate vhdl top
level and use verilog system tasks to generate waveform files? What
are the command line then to compile&elab and invoke the
simulator(ncsim) ?


many thanks!!
Metin

 

[Jim Wu]

How can i generate *trn *dsn. files with vhdl. Whats the most straight
and sophisticated way to do this. I don't want to use nclaunch nor
interactive ncsim tcl shell. I want to run the ncsim and later if
needed check the waveforms.

Check "-input" option of ncsim.

would it work if i write a verilog testbench and instantiate vhdl top
level and use verilog system tasks to generate waveform files?

If you have mixed language license, you can simulate your design. I don't
think the system tasks will work on the VHDL portion of your design though.

What are the command line then to compile&elab and invoke the
simulator(ncsim) ?

ncvlog
ncvhdl
ncelab
ncsim


HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

Metin Yerlikaya wrote:

Now i have to use vhdl and ncvhdl. Is it true that above method is
not
possible for vhdl testbenchs.

I think it is true.

How can i generate *trn *dsn. files with vhdl. Whats the most
straight
and sophisticated way to do this. I don't want to use nclaunch nor
interactive ncsim tcl shell. I want to run the ncsim and later if
needed check the waveforms.

I think a tcl probe command is the easiest way to do this.
As someone else noted, you do not have to run interactively
to execute tcl commands. You can use the -input option to
the simulator to execute some tcl commands before starting
the simulation.

would it work if i write a verilog testbench and instantiate vhdl top
level and use verilog system tasks to generate waveform files? What
are the command line then to compile&elab and invoke the
simulator(ncsim) ?

It might work. I don't know whether $recordvars will go
down into the VHDL part of the design or not. I suspect
it would be more complex than executing a tcl script at
the start of the simulation.