NCVHDL/NCELAB and Recursive Instantiation

[Anand P Paralkar]

Hi,

I have written a model to calculate the parity of a 'n' bit vector (n is
even). The idea is to recursively generate the tree until the span of the
tree covers the entire length of 'n'. A tree that covers a vector of
length n requires a log2 levels/height. Vice-versa, a tree with level
'l' can calculate the parity of a (2 ** l) bit vector.

So much for the theory. Here is the code:

-------------------------------------------------------------------------
entity pargen is
generic (level : positive := 5);
port (z : out bit;
d : in bit_vector (0 to ((2**level) - 1)));
end entity pargen;

architecture recur of pargen is
begin
degenerate_tree : if (level = 0) generate
z <= d(0);
end generate degenerate_tree;

compound_tree : if (level > 0) generate
signal lin, rin : bit;
begin
par_gate : entity work.xorg(gatel)
port map (lin, rin, z);

sub_tree_l : entity work.pargen(recur)
generic map (level - 1)
port map (z => lin, d => d(0 to ((2**(level - 1)) - 1)));

sub_tree_r : entity work.pargen(recur)
generic map (level - 1)
port map (z => rin, d => d((2**(level - 1)) to ((2**level) - 1)));

end generate compound_tree;
end architecture recur;
--------------------------------------------------------------------------

The entity xorg is a model for an xor gate. It is compiled and present
in the work library.

The pargen model is instantiated in a test bench as follows:

--------------------------------------------------------------------------
entity tb_pargen is
end entity tb_pargen;

architecture test of tb_pargen is
signal parout : bit;
signal d : bit_vector (0 to 15);
begin

DUT : entity work.pargen(recur)
generic map (4)
port map (parout, d);
end architecture test;
---------------------------------------------------------------------------

Problem: The test bench compiles correctly but elaboration (ncelab) gives
the following error:

ncelab -v93 -messages WORK.TB_PARGEN:TEST
ncelab: v03.30.(s012): (c) Copyright 1995 - 2002 Cadence Design Systems,
Inc.
Elaborating the design hierarchy:
Simulation execution error detected: range constraint violation
source file: ex14_14.vhd, line = 2, position = 15
Unknown stream type (in design unit WORK.PARGEN:RECUR)
Direct instantiation elaboration for instance:
:tb_pargen(test)UT@pargen(recur):compound_tree:sub_tree_l
ncelab: *E,CUELEE: execution error prevents further elaboration.



Could somebody please explain what the problem could be. (Note: This
circuit synthesizes correctly (using Synplify Pro).)

Thanks,
Anand

 

[Eyck Jentzsch]

Anand P Paralkar wrote:

Hi,

I have written a model to calculate the parity of a 'n' bit vector (n is
even). The idea is to recursively generate the tree until the span of the
tree covers the entire length of 'n'. A tree that covers a vector of
length n requires a log2 levels/height. Vice-versa, a tree with level
'l' can calculate the parity of a (2 ** l) bit vector.

So much for the theory. Here is the code:
......

Could somebody please explain what the problem could be. (Note: This
circuit synthesizes correctly (using Synplify Pro).)

Thanks,
Anand

I seems to be a bug in NCSim with respect to the VHDL93 direct

instantiation; if you rewrite your code:
-----------------------------------------------------------
architecture recur of pargen is
component pargen is
generic (level : natural := 5);
port (z : out bit;
d : in bit_vector (0 to ((2**level) - 1)));
end component pargen;
begin
degenerate_tree : if (level = 0) generate
z <= d(0);
end generate degenerate_tree;

compound_tree : if (level > 0) generate
signal lin, rin : bit;
begin
par_gate : entity work.xorg(gatel)
port map (lin, rin, z);

sub_tree_l : pargen
generic map (level-1)
port map (z => lin, d => d(0 to ((2**(level - 1)) - 1)));

sub_tree_r : pargen
generic map (level-1)
port map (z => rin, d => d((2**(level - 1)) to 2**level - 1));

end generate compound_tree;
end architecture recur;
-----------------------------------------------------------
then it runs well.

-Eyck

 

[Mike Treseler]

Could somebody please explain what the problem could be. (Note: This
circuit synthesizes correctly (using Synplify Pro).)

Thanks,
Anand

OK. It compiles with one warning about drivers.
Let's try to sim it:

# 5.7c

# vsim -c tb_pargen
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading work.tb_pargen(test)
# Loading work.pargen(recur)
# Loading work.xorg(gate1)
# ** Fatal: (vsim-3421) Value 0 for level is out of range 1 to 2147483647.

so let's change positve to natural:

generic (level : natural := 5);

# 5.7c

# vsim -c tb_pargen
# // ModelSim SE VHDL 5.7c Mar 1 2003 Linux 2.4.19-4GB
# //
# // Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# // All Rights Reserved.
# // UNPUBLISHED, LICENSED SOFTWARE.
# // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading work.tb_pargen(test)
# Loading work.pargen(recur)
# Loading work.xorg(gate1)
VSIM 1>

That makes modelsim happy.

-- Mike Treseler