ncverilog warnings on fanin

[Verictor]

Hi,

I have a circuit having simulation warnings from ncverilog:

Implicit wire has no fanin

I look at these particular warnings. Some of the involved wires are
direct connecting between sub-modules while some others are connecting
as external inputs. What do the warnings mean? Do these warnings mean
these wires are floating? .

Thanks.

 

Verictor wrote:

I have a circuit having simulation warnings from ncverilog:

Implicit wire has no fanin

I look at these particular warnings. Some of the involved wires are
direct connecting between sub-modules while some others are connecting
as external inputs. What do the warnings mean? Do these warnings mean
these wires are floating? .

Yes, it means that these wires are floating, because
they have no drivers.

This warning is produced to help you avoid a common
mistake. In Verilog, if you use an undeclared name in
the port of a module instance, it is implicitly declared
as a wire. But this means that if you misspell the name
of a wire you are connecting to an instance port list, you
will not get an error to tell you that you made a mistake.
It will get implicitly declared as a new wire that is not
connected to the rest of the design. This can be very
hard to debug.

If an implicit wire does not have a driver, it is likely that
you have made this mistake, and NC-Verilog gives you
a warning to help you find it.

You can get extended descriptions of what warnings
mean in NC-Verilog by using the nchelp utility, with
the name of the executable and the error code. For
example, if you type in

nchelp ncelab CSINFI

or

nchelp ncverilog CSINFI

you will get the following explanation:

ncelab/CSINFI =
The indicated net has no explicit declaration and it has no
drivers.
Although this is legal Verilog, it often results from a
misspelling in
the net name or some other mistake in the Verilog code. This
warning
is issued to alert the designer to check for a coding error.

 

[Utku Özcan]

Yes they are floating. It means that the wires are undeclared and they
have no driver, ie. there is not any Verilog statement in your code
which stimulates this implicit wire. Example:

ram u1 (
.cs (cs_enable)
...
);

ram u2 (
.cs (cs_enable)
...
);

... and if this "cs_enable" is not declared anywhere (ie. implicit
wire) in the scope where RAMs are instantiated, then you get this
warning.

It might be a design error, so don't ignore this warning.

Utku

On 31 Jan., 19:14, "Verictor" <stehu...@gmail.com> wrote:

Hi,

I have a circuit having simulation warnings from ncverilog:

Implicit wire has no fanin

I look at these particular warnings. Some of the involved wires are
direct connecting between sub-modules while some others are connecting
as external inputs. What do the warnings mean? Do these warnings mean
these wires are floating? .

Thanks.

 

[Verictor]

Thanks folks. Yes, that was caused my mis-typing. Shouldn't ignore
this warning.

On Jan 31, 4:18 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote:

Yes they are floating. It means that the wires are undeclared and they
have no driver, ie. there is not any Verilog statement in your code
which stimulates this implicit wire. Example:

ram u1 (
.cs (cs_enable)
...
);

ram u2 (
.cs (cs_enable)
...
);

.. and if this "cs_enable" is not declared anywhere (ie. implicit
wire) in the scope where RAMs are instantiated, then you get this
warning.

It might be a design error, so don't ignore this warning.

Utku

On 31 Jan., 19:14, "Verictor" <stehu...@gmail.com> wrote:



Hi,

I have a circuit having simulation warnings from ncverilog:

Implicit wire has no fanin

I look at these particular warnings. Some of the involved wires are
direct connecting between sub-modules while some others are connecting
as external inputs. What do the warnings mean? Do these warnings mean
these wires are floating? .

Thanks.- Hide quoted text -

- Show quoted text -

 

Verictor wrote:

Thanks folks. Yes, that was caused my mis-typing. Shouldn't ignore
this warning.

If you are not deliberately relying on implicit net
declarations, there is a better way to catch such
mis-typing. You can turn off these implicit net
declarations with a compiler directive, after which
any unrecognized identifiers will be flagged as
an error. However, you should be aware that
the common practice of only declaring ports as
input/output/inout and letting them be implicitly
assumed to be nets will also become an error.

The directive is

`default_nettype none