P
prav
Guest
Hi all,
I am using NC verilog as the simulator tool for my simulations.
My testbench code is in VERA and RTL in verilog. I have generated the
..vro file and the vshell file. what is the next step to simulate my
RTL along with the VERA using NC verilog.
Thanks in advance,
Prav
I am using NC verilog as the simulator tool for my simulations.
My testbench code is in VERA and RTL in verilog. I have generated the
..vro file and the vshell file. what is the next step to simulate my
RTL along with the VERA using NC verilog.
Thanks in advance,
Prav