E
eda_employee
Guest
For a large mixed-language (VHDL-93, Verilog-2001) SoC design,
I've noticed that dumping the entire testbench hieararchy (from top)
seems to take a very long time (surprise surprise...)
But there is a large performance difference between dumping a
Debussy-compatible database (*.fsdb) and Signalscan/Simvision (*.shm)
If I use NCSIM's built-in $shm_open/$shm_probe, the simulation runs
much faster. Is this what everyone else is seeing?
(I'm guessing that shm-output uses NCSIM's internal-routines, and
aren't bottlenecked by the PLI/VPI external-interface.)
I've noticed that dumping the entire testbench hieararchy (from top)
seems to take a very long time (surprise surprise...)
But there is a large performance difference between dumping a
Debussy-compatible database (*.fsdb) and Signalscan/Simvision (*.shm)
If I use NCSIM's built-in $shm_open/$shm_probe, the simulation runs
much faster. Is this what everyone else is seeing?
(I'm guessing that shm-output uses NCSIM's internal-routines, and
aren't bottlenecked by the PLI/VPI external-interface.)