A
A2500
Guest
Hello every body!
I generated a verlig file by Xilinx Core generator, I need to simulate
it in NCLaunch.
I tried to Edit "cds.lib" file with following Parameters:-
define SIMPRIMS C:/Xilinx/verilog/src/simprims
define CoreLib C:/Xilinx/verilog/src/XilinxCoreLib
but when I try to Elaborate the Generated Module it gives an error
saying that can not view the list CORELIB .......... (System Error)
anybody can help?
thanks in advance,
mirzaaur
I generated a verlig file by Xilinx Core generator, I need to simulate
it in NCLaunch.
I tried to Edit "cds.lib" file with following Parameters:-
define SIMPRIMS C:/Xilinx/verilog/src/simprims
define CoreLib C:/Xilinx/verilog/src/XilinxCoreLib
but when I try to Elaborate the Generated Module it gives an error
saying that can not view the list CORELIB .......... (System Error)
anybody can help?
thanks in advance,
mirzaaur