ncelab: *W,SDFINF warning when back annotating SDF

[jay]

Hello all,

I have a module named moduleA, I have a testbench moduleA_tb and
instantiate moduleA_uut inside, and use $sdfannotate ("delay.sdf") to
back annotate the design.

I use ncverilog to run timing simulation, and got below warnings:
ncelab: *W,SDFINF: Instance moduleA not found at scope level <top-
level> <./delay.sdf, line 283422>.

The delay.sdf is gotten from ASIC team, I found the instance names in
it are moduleA.i1.xxx etc. I think I need to change all of them to
moduleA_uut.i1.xxx, then I don't get the SDFINF warning when rerun the
simulation, but thousands of "ncelab: *W,SDFNEP: Unable to annotate to
non-existent path (xxx)" warnings and "Warning! Timing violation"
during simulation.

I'm not very familiar with simulation, am I doing the right thing?

 

On Oct 12, 2:29 am, jay <heavenf...@gmail.com> wrote:

I have a module named moduleA, I have a testbench moduleA_tb and
instantiate moduleA_uut inside, and use $sdfannotate ("delay.sdf") to
back annotate the design.

I don't know anything about SDF annotation, but I can make some
guesses.

I use ncverilog to run timing simulation, and got below warnings:
ncelab: *W,SDFINF: Instance moduleA not found at scope level <top-
level> <./delay.sdf, line 283422>.

It is trying to find your moduleA at the top of the design. But in
your version of the design, it isn't at the top any more (and isn't
named moduleA). I assume that is the problem.

The delay.sdf is gotten from ASIC team, I found the instance names in
it are moduleA.i1.xxx etc. I think I need to change all of them to
moduleA_uut.i1.xxx, then I don't get the SDFINF warning when rerun the
simulation, but thousands of "ncelab: *W,SDFNEP: Unable to annotate to
non-existent path (xxx)" warnings and "Warning!  Timing violation"
during simulation.

I suspect you would have to change moduleA to moduleA_tb.moduleA_uut,
not just moduleA_uut.

However, I doubt that modifying the SDF file is the proper way to do
this. SDF annotation has to deal with this all the time, so there has
to be an easy way to do this. You also have to be able to apply SDF
annotation for multiple DUTs, when they are incorporated into larger
systems. I would guess that you can add another argument to
$sdf_annotate to tell it what subpart of the design the SDF applies
to. Something like $sdf_annotate("delay.sdf",
moduleA_tb.moduleA_uut). But since I am just guessing based on what
seems to make sense, you should consult your documentation or another
more knowledgeable engineer.