nc-verilog: illegal concatenation error

[Pete]

I'm having problems with the nc-verilog tool. The following line of
code:

foo[7:0] <= {addr[0][15:8]};

generates a "illegal concatenation syntax" error with version
5.00-p001.

I'm using the +ncieee1364 option on the command line.

This code compiles and runs with modelsim. Is there another switch I
should be using with nc-verilog?

Thanks,

Pete

 

[Rudolf Usselmann]

Petrov_101@hotmail.com (Pete) wrote in message news:<632dfd04.0308061253.325d49b8@posting.google.com>...

I'm having problems with the nc-verilog tool. The following line of
code:

foo[7:0] <= {addr[0][15:8]};

generates a "illegal concatenation syntax" error with version
5.00-p001.

I'm using the +ncieee1364 option on the command line.

This code compiles and runs with modelsim. Is there another switch I
should be using with nc-verilog?

Thanks,

Pete

Can't do bit selects on memories ...
try:

wire [15:0] temp;

assign temp = addr[0];
assign foo[7:0] = temp[15:8];

You don't need the concatenation operator here at
all, unless I am missing something ...

Regards,
rudi
--------------------------------------------------------
www.asics.ws --- Solutions for your ASIC/FPGA needs ---
----------------- FPGAs * Full Custom ICs * IP Cores ---
FREE IP Cores --> http://www.asics.ws/ <-- FREE IP Cores

 

[Pete]

russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0308070142.77496213@posting.google.com>...

Can't do bit selects on memories ...
try:

wire [15:0] temp;

assign temp = addr[0];
assign foo[7:0] = temp[15:8];

You don't need the concatenation operator here at
all, unless I am missing something ...

Regards,
rudi

Thanks for the info. I was thinking of doing something like that.
Cadence replied back to my question and mentioned that the current
tools don't support all of the features of verilog 2001 yet. Guess
I'll have to rewrite this part of the code.

Thanks,
Pete

 

[Steven Sharp]

Petrov_101@hotmail.com (Pete) wrote in message news:<632dfd04.0308061253.325d49b8@posting.google.com>...

I'm having problems with the nc-verilog tool. The following line of
code:

foo[7:0] <= {addr[0][15:8]};

generates a "illegal concatenation syntax" error with version
5.00-p001.

Bit-selects and part-selects of memory (i.e. array) elements was
not legal in the Verilog-1995 standard. To do this you would
have to assign the memory word to a temporary vector variable
and then do a part-select out of that.

The ability to do bit-selects and part-selects of array elements
was added in the Verilog-2001 standard. This extension has not
been implemented yet in version 5.0 of NC-Verilog. I believe that
version 5.1, which is in beta test, may allow bit-selects, but
not part-selects. This may seem odd, but is a consequence of
adding multi-dimensional arrays of regs (another Verilog-2001
extension) in version 5.1.

 

[xno]

Bit-selects and part-selects of memory (i.e. array) elements was
not legal in the Verilog-1995 standard. To do this you would
have to assign the memory word to a temporary vector variable
and then do a part-select out of that.

The ability to do bit-selects and part-selects of array elements
was added in the Verilog-2001 standard. This extension has not
been implemented yet in version 5.0 of NC-Verilog. I believe that
version 5.1, which is in beta test, may allow bit-selects, but
not part-selects. This may seem odd, but is a consequence of
adding multi-dimensional arrays of regs (another Verilog-2001
extension) in version 5.1.

I find it irritating that different vendors support different parts of the
Verilog-2001 standard. For example, Synopsys Design Compiler
2003.06-2 still doesn't support the 'localparam' keyword (and
neither does Cadence Ambit/PKS 5.) Yet others have supported
this for a while.

But I'm grateful for the signed arithmetic support (>>&gt. Everyone
seems to support that, and in my work, that actually turns out to
be very convenient. (But I sure would like to have multidim arrays!)