NC verilog and specify block query

A

Anshul Bansal

Guest
Hello all

I am trying to use the following specify block in my program.

reg nX1, nX0, X1, X0;

specify

specparam D1=10;
specparam D2=20;
(A0,A1,B0,B1,Xe,en *> nX1) = D1;
(A0,A1,B0,B1,Xe,en *> nX0) = D1;
(A0,A1,B0,B1,Xe,en *> X0) = D2;
(A0,A1,B0,B1,Xe,en *> X1) = D2;

endspecify

When I try to compile this entire design in NC Verilog simulator then
it gives me an error that
"Register Encountered in specify block".

does this mean I can't use registers in specify block.

Moreover when I compile the same design in Modelsim simulator, it
compiles properly without giving any error.

Please help asap.

thanks

anshul
 

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