NC sim error with mixed mode

Hello
I have a VHDL model and using a verilog testbench and using ncsim for
mixedmode simulation. I get this error

ncelab: *W,CUDEFB: default binding occurred for component instance
(testbench.PUSB21) with desig
n unit (NC_LIB.USB2:BEHAVIORAL).
Building instance overlay tables: ....................
initial $readmemb("pusb2.vec",tstvector);
|
ncelab: *W,MEMODR (./tb_pusb2.v,75|38): $readmem default memory order
incompatible with IEEE1364
..
Done
Generating native compiled code:
ncvhdl_cg: *internal* (gc_storei - pib s2).
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
ncelab: *E,CUVCGF: Code generation for
I.nc_lib.usb2.A.behavioral.vhdl.a.lnx86.151.ast <0x4d9da9
f4> failed.
ncelab: *F,CGFAIL: Code generation failed for one or more modules.
TOOL: ncelab 05.10-p004: Exiting on Jun 20, 2006 at 17:39:49
(total: 00:00:02)

Has anyone seen this kind of error? Please let me know

Thanks
krithiga