Narrow pulse width generation

[Tom Sanders]

Hello,

I am trying to use a rising edge of a clock to generate a
sub-nanosecond pulsewidth. Does anyone know of any components out
there that can be used to achieve this?

Thanks

 

[Boris Mohar]

On 1 Apr 2004 17:56:37 -0800, engrwebmaster@yahoo.com (Tom Sanders) wrote:

Hello,

I am trying to use a rising edge of a clock to generate a
sub-nanosecond pulsewidth. Does anyone know of any components out
there that can be used to achieve this?

Thanks

Step recovery diode or SRD.

--

Boris Mohar

 

[CBarn24050]

I am trying to use a rising edge of a clock to generate a
sub-nanosecond pulsewidth. Does anyone know of any components out
there that can be used to achieve this?

An xor gate will produce a pulse on each edge, width is equal to the time
difference between the ip pulse to each input. You can add an and gate to
supress the extra pulse.

 

[mike]

Tom Sanders wrote:

Hello,

I am trying to use a rising edge of a clock to generate a
sub-nanosecond pulsewidth. Does anyone know of any components out
there that can be used to achieve this?

Thanks

How sub?
How big?
Are you ever gonna need a second one? How soon?

If you look into the emitter of an emitter follower, you
can convince yourself that a first order approximation to
the behavior is a resistor and inductor in parallel.
If you stuff in a current step, you get a voltage pulse.
It's amplitude and tempco compatible with the old MECL III logic
family.

The interesting part of the behavior is that when you turn off
the current, the (virtual) inductor goes away. Makes a way cool short pulse
generator without all the nasty ringing properties of a shorted
transmission line or a real inductor. And if you drive it too fast
(rep rate) it just becomes sorta transparent. One-port devices are neat.

For a given state of technology, you can probably get shorter pulses
than with a gate-delay differientiator.
I used it at rep rates of 250 MHz. 30 years ago.

mike

--
Return address is VALID.
Bunch of stuff For Sale and Wanted at the link below.
Toshiba & Compaq LiIon Batteries, Test Equipment
Honda CB-125S $800 in PDX
Yaesu FTV901R Transverter, 30pS pulser
Tektronix Concept Books, spot welding head...
http://www.geocities.com/SiliconValley/Monitor/4710/

 

[Tom Sanders]

Thanks, I am looking to create a 140-150ps pulse width. Can this be
done using the XOR and AND gates that you recommended?

Thanks in advance for your help.

-Tom

cbarn24050@aol.com (CBarn24050) wrote in message news:<20040401212428.18086.00000547@mb-m03.aol.com>...

I am trying to use a rising edge of a clock to generate a
sub-nanosecond pulsewidth. Does anyone know of any components out
there that can be used to achieve this?


An xor gate will produce a pulse on each edge, width is equal to the time
difference between the ip pulse to each input. You can add an and gate to
supress the extra pulse.

 

[Hal Murray]

Thanks, I am looking to create a 140-150ps pulse width. Can this be
done using the XOR and AND gates that you recommended?

That's pretty exciting. What are you going to do with it?
What do you use for a buffer/amplifier?

140 ps is 7 gigabits. You might be able to make that with
a parallel to serial converter - SERDES. You need one that lets
you feed in the raw bits rather than doing the 8B/10B type
encoding for you.

Xilinx gets up to 3 gigabits in their RocketIO in their Virtex Pro
family. The Pro X line says 10 gigabits, but I don't think they
are available yet.

I took a quick scan at OnSemi's ECLInPS line. It's what I think
of as the top end of simple gates. They say 3 gigahertz toggle
freq for the MC100EP08 and a typical rise/fall time of 130 ps.
So that's off by a factor of 2 from your target.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.