NAND flash interface?

[guille]

Hello there,

Has anyone implemented a NAND interface in a PLD? I don't mean a
'smart' NAND controller, just an interface that lets you toggle ALE,
CLE, CE externally and do read/write accesses to the NAND ports.

Thanks,
Guillermo Rodriguez

 

[Mark Ng]

Hi Guillermo,

Take a look at Xilinx Application Note, XAPP354 located at:

http://direct.xilinx.com/bvdocs/appnotes/xapp354.pdf

Hope that helps!
Mark

guille wrote:

Hello there,

Has anyone implemented a NAND interface in a PLD? I don't mean a
'smart' NAND controller, just an interface that lets you toggle ALE,
CLE, CE externally and do read/write accesses to the NAND ports.

Thanks,
Guillermo Rodriguez

 

[rickman]

guille wrote:

Hello there,

Has anyone implemented a NAND interface in a PLD? I don't mean a
'smart' NAND controller, just an interface that lets you toggle ALE,
CLE, CE externally and do read/write accesses to the NAND ports.

Thanks,
Guillermo Rodriguez

I'm not sure what you are looking for. If you control the ALE, etc,
then you are talking directly to the NAND part and don't need a
controller. Or are you asking how to generate ALE, CLE and the other
inputs that are not typical MCU controls? The timing for these control
inputs are the same as for what would be the address inputs on a NOR
flash part. So I just tie them to address lines. The MCU then writes a
command word by writing to an address that raises CLE and lowers ALE.
It writes the address register by writing the data address to the
address that lowers the CLE signal and raises the ALE signal.

I don't think you need a PLD for this unless you use it to decode the
address to generate the CE signal.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX