N-Input Gate Using Loop or Generate

I have been thinking of making generic gates for a library. These
would be single N-input gates. A gate is easy enough to code, but I
have not been able think of a way to do this using a generate or other
loop statement so that a single component declaration would work for
each gate type (and, or, etc.). An instantiated component would look
like this (I might put some extras in to set polarity of each input and
the output):

and_gate_1 : and_gate
generic map( N => 3 ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic


Suggestions?

Best regards,

Charles

 

Jonathan,

Excellent idea! Replies like yours are what makes this such a good
group.

Thank you,

Charles

 

Thanks, everyone for your help. I thought you might like to see an
example of what I actually put in my library:

--A_pol sets the "polarity" of each input; if A_pol( i ) = '0' then
A(i) is low assertive, if A_pol(i) = '1' then A(i) is high assertive.
--In a similar manner, Y_pol sets the polarity of the output Y.

entity or_gate is
generic ( N : positive );
port ( A_pol : in std_logic_vector( N - 1 downto 0 ) := ( others =>
'1' );
Y_pol : in std_logic := '1';
A : in std_logic_vector( N - 1 downto 0 );
Y : out std_logic
);
end;

architecture P of or_gate is
begin
process ( A, A_pol, Y_pol )
variable result: std_logic;
begin
result := '0';
for i in A'range loop
result := result or ( ( not A_pol( i ) ) xor A( i ) );
end loop;
Y <= ( not Y_pol ) xor result;
end process;
end;
----------------------------------------------------------------------------------------
Charles