n bit adder

[Lilmiss]

Hi,
The question is to write VHDL code for an n-bit incrementor circuit.
Could you provide any suggestions
for improving my code?


Generate:

library IEEE;
use IEEE.STD_LOGIC_1164.all;


Entity incrementer_st is
generic(width : positive);
port(A : in std_logic_vector (width-1 downto 0) ;
C0 : in std_logic;
Cn : out std_logic;
S : out std_logic_vector(width-1 downto 0));
End incrementer_st;



architecture incrementer_st of incrementer_st is
component incrementer
port ( A : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal C : std_logic_vector(0 to width);
begin
g1 : for b in 0 to width-1 generate
U1: incrementer port map(A=>A(b), Cin=> C(b), S=>S(b), Cout=>C(b+1));
end generate;

C(0) <= C0;
Cn <= C(width);
end incrementer_st;


--Also, could you clarify the difference between generic and generate
statements (silly question I know)

10x