My type in main entity

[zlotawy]

Hi,
I'd like to create entity like this:

entity top1 is

generic (
NUMBER : Integer := 14
);

PORT(
P_IN_DAC : IN my_type(NUMBER -1 downto 0)

);
end top1;

and my_type is:

type my_type is array(natural range <&gt of std_logic_vector(20 downto 0) ;

Compilation has errors. Where do I have to declare my type? Is it possible
to create input port of FPGA with own type?


Thanks,
zlotawy

 

[Macias Wojtas]

Compilation has errors. Where do I have to declare my type?

You can declare your type in your own package and use this packed in file
where you have this input.

Is it possible to create input port of FPGA with own type?

Of course it is possible, but your type has to be synthesable eg. array of
STD_LOGIC_VECTOR.

Best regards

Macias

 

[Andy]

On Aug 7, 4:46 pm, "Macias Wojtas" <wojt...@poczta.onet.pl> wrote:

Compilation has errors. Where do I have to declare my type?

You can declare your type in your own package and use this packed in file
where you have this input.

Is it possible to create input port of FPGA with own type?

Of course it is possible, but your type has to be synthesable eg. array of
STD_LOGIC_VECTOR.

Best regards

Macias

There are far more composite types than arrays of SLV that are
synthesizable. Records and arrays of boolean, bit, integer, other
records and other arrays, etc., are all synthesizable.

They type declaration needs to be in a package that is referenced in
the context clause of the entity (i.e. in a use statement). Of course
what ever instantiates that entity (or its component), like a test
bench, will also have to reference the package.

Andy

 

[Macias Wojtas]

"Andy" <jonesandy@comcast.net> wrote in message
news:1186580519.228322.165120@e16g2000pri.googlegroups.com...

On Aug 7, 4:46 pm, "Macias Wojtas" <wojt...@poczta.onet.pl> wrote:
Of course it is possible, but your type has to be synthesable eg. array
of STD_LOGIC_VECTOR

There are far more composite types than arrays of SLV..

I know that's why I used 'e.g.' befor 'array of STD_LOGIC_VECTOR'.

Best regards

Macias

 

[Andy]

On Aug 8, 3:03 pm, "Macias Wojtas" <wojt...@poczta.onet.pl> wrote:

"Andy" <jonesa...@comcast.net> wrote in message

news:1186580519.228322.165120@e16g2000pri.googlegroups.com...

On Aug 7, 4:46 pm, "Macias Wojtas" <wojt...@poczta.onet.pl> wrote:
Of course it is possible, but your type has to be synthesable eg. array
of STD_LOGIC_VECTOR

There are far more composite types than arrays of SLV..

I know that's why I used 'e.g.' befor 'array of STD_LOGIC_VECTOR'.

Best regards

Macias

Easy there, buddy; just clarifying.

Andy

 

[zlotawy]

Uzytkownik "Andy" <jonesandy@comcast.net> napisal w wiadomosci
news:1186580519.228322.165120@e16g2000pri.googlegroups.com...

I cretated this code:

package pcg is
constant DATA_SIZE : Integer := 20;
type my_type is array(natural range <&gt of std_logic_vector(DATA_SIZE-1
downto 0) ;
end pcg ;

entity top1 is

generic (
NUMBER : Integer := 14
);

PORT(
P_I_CLK : IN std_logic;
P_IN_DAC : IN my_type(NUMBER -1 downto 0)

);
end top1;



and I got error:
Undefined symbol 'std_logic'.


What is wrong?

Thanks
zlotawy

 

[Mike Treseler]

zlotawy wrote:

What is wrong?
missing library declarations and references

-- Mike Treseler
______________________________________________
library ieee;
use ieee.std_logic_1164.all;
package pcg is
constant DATA_SIZE : integer := 20;
type my_type is array(natural range <&gt
of std_logic_vector(DATA_SIZE-1 downto 0);
end pcg;

library ieee;
use ieee.std_logic_1164.all;
use work.pcg.all;
entity top1 is
generic (
NUMBER : integer := 14
);

port(
P_I_CLK : in std_logic;
P_IN_DAC : in my_type(NUMBER -1 downto 0)
);
end top1;

 

[Andy]

On Aug 11, 12:50 pm, "zlotawy" <spaw...@wp.NO_SPAM.pl> wrote:

Uzytkownik "Andy" <jonesa...@comcast.net> napisal w wiadomoscinews:1186580519.228322.165120@e16g2000pri.googlegroups.com...



I cretated this code:

package pcg is
constant DATA_SIZE : Integer := 20;
type my_type is array(natural range <&gt of std_logic_vector(DATA_SIZE-1
downto 0) ;
end pcg ;

entity top1 is

generic (
NUMBER : Integer := 14
);

PORT(
P_I_CLK : IN std_logic;
P_IN_DAC : IN my_type(NUMBER -1 downto 0)

);
end top1;

and I got error:
Undefined symbol 'std_logic'.

What is wrong?

Thanks
zlotawy

You created a package, and it is compiled into the library when you
compile the file, but you did not tell your entity to reference that
(or any other library or) package. There is no "file" scope in vhdl.
Just because a package is declared in the same file as the entity,
does not mean that the entity has automatic visibility of that
package.

Andy