Muxes : 64X1

Gary Olson · May 7, 2004

Question I have is I need a 42X1 Mux 
Actually I am muxing 42 16 bit databusses. The Timing is critical 
because the 42 16 bit words are read by a microcontroller. I am wondering the best way to MUX theses signals. I could use a 64X1 mux and syntesize out unused logic. Or I could use a 32X1, 16X1 with a 2X1 to merge the two muxed data paths. Does it make any difference at all what I do? Any other alternative approaches? Thank You, 
Gary Olson

Gary Olson · May 7, 2004

I meant the timing is not critical because I am reading the Mux output with a Microcontroller.

Symon · May 7, 2004

Gary,
Ken Chapman of Xilinx wrote a TechXclusive about Multiplexers. It's worth a
read.
cheers, Syms.

Gary Olson · May 7, 2004

Here is my VHDL library IEEE; 
use IEEE.STD_LOGIC_1164.all; entity MUX42 is 
port ( 
dIn_0 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_1 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_2 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_3 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_4 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_5 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_6 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_7 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_8 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_9 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_10 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_11 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_12 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_13 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_14 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_15 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_16 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_17 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_18 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_19 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_20 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_21 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_22 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_23 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_24 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_25 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_26 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_27 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_28 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_29 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_30 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_31 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_32 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_33 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_34 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_35 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_36 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_37 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_38 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_39 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_40 : in STD_LOGIC_VECTOR (15 downto 0); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_41 : in STD_LOGIC_VECTOR (15 downto 0); 
sel_0 : in STD_LOGIC; -- select mux input 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sel_1 : in STD_LOGIC; -- select mux input 
sel_2 : in STD_LOGIC; -- select mux input 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sel_3 : in STD_LOGIC; -- select mux input 
sel_4 : in STD_LOGIC; -- select mux input 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sel_5 : in STD_LOGIC; -- select mux input 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dOut : out STD_LOGIC_VECTOR (15 downto 0) 
&nbsp;&nbsp;&nbsp;&nbsp

; 
end MUX42; --}} End of automatically maintained section architecture MUX42 of MUX42 is 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;signal adr: std_logic_vector(5 downto 0); 
begin 
&nbsp;&nbsp;&nbsp;&nbsp;adr <= sel_5 & sel_4 & sel_3 & sel_2 & sel_1 & sel_0; with adr select dOut<= 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_0 when "000000", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_1 when "000001", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_2 when "000010", 
dIn_3 when "000011", 
dIn_4 when "000100", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_5 when "000101", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_6 when "000110", 
dIn_7 when "000111", 
dIn_8 when "001000", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_9 when "001001", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_10 when "001010", 
dIn_11 when "001011", 
dIn_12 when "001100", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_13 when "001101", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_14 when "001110", 
dIn_15 when "001111", 
dIn_16 when "010000", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_17 when "010001", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_18 when "010010", 
dIn_19 when "010011", 
dIn_20 when "010100", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_21 when "010101", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_22 when "010110", 
dIn_23 when "010111", 
dIn_24 when "011000", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_25 when "011001", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_26 when "011010", 
dIn_27 when "011011", 
dIn_28 when "011100", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_29 when "011101", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_30 when "011110", 
dIn_31 when "011111", 
dIn_32 when "100000", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_33 when "100001", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_34 when "100010", 
dIn_35 when "100011", 
dIn_36 when "100100", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_37 when "100101", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_38 when "100110", 
dIn_39 when "100111", 
dIn_40 when "101000", 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dIn_41 when

Ray Andraka · May 9, 2004

Depending on your design, you could put these in a BRAM and
then have the uP read the BRAM. Works well for reading back
values written to registers by the uP that you want to be
able to read back, in which case you have both your register
and the BRAM where the BRAM acts as a shadow register who's
sole purpose is to provide readback data to the uP. For
registers written by the FPGA, you can work the registers
like a shift register to write them into a BRAM, then have
the uP read the BRAM. It gains you random access without
the muxes and wires.

Gary Olson wrote:

Question I have is I need a 42X1 Mux
Actually I am muxing 42 16 bit databusses. The Timing is
critical
because the 42 16 bit words are read by a microcontroller.
I am wondering the best way to MUX theses signals. I could
use a 64X1 mux and syntesize out unused logic.

Or I could use a 32X1, 16X1 with a 2X1 to merge the two
muxed data paths.

Does it make any difference at all what I do? Any other
alternative approaches?

Thank You,
Gary Olson

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759

Muxes : 64X1

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