mux code

[rajan]

Hi,

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

I would appreciate your help.

Thank you.

rajan

 

[Ralf Hildebrandt]

rajan wrote:

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

"sel" is not in sensitivity list, therefore in simulation nothing will
happen, if no input, but sel changes.

What you have done is modelling 8 Latches (out_1 to out_8). Let me
describe, what I mean with the example out_1: out_1 is driven with in_1,
when sel='1'. If sel='0' nothing will happen to out_1. This means, out_1
holds its old value. This is a "level sensitive register" aka Latch.

The following code describes 4 two-to-one muxes (out_1 to out_4):

process (sel, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_1 <= in_5;
out_2 <= in_6;
out_3 <= in_7;
out_4 <= in_8;
end if;
end process;


Ralf

 

[rajan]

Hi Ralf,

Thank you for your great help. Is there a better way to write this so that
it synthesizes well (or synthesizes without latches).


"Ralf Hildebrandt" <Ralf-Hildebrandt@gmx.de> wrote in message
news:2pk1ioFlmtdlU1@uni-berlin.de...

rajan wrote:

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

"sel" is not in sensitivity list, therefore in simulation nothing will
happen, if no input, but sel changes.

What you have done is modelling 8 Latches (out_1 to out_8). Let me
describe, what I mean with the example out_1: out_1 is driven with in_1,
when sel='1'. If sel='0' nothing will happen to out_1. This means, out_1
holds its old value. This is a "level sensitive register" aka Latch.

The following code describes 4 two-to-one muxes (out_1 to out_4):

process (sel, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_1 <= in_5;
out_2 <= in_6;
out_3 <= in_7;
out_4 <= in_8;
end if;
end process;


Ralf

 

[Ralf Hildebrandt]

rajan wrote:

Thank you for your great help. Is there a better way to write this so that
it synthesizes well (or synthesizes without latches).

Then let us know, what do you really want! Which input signals (plural -
not singular!) should be muxed to which output (singular, not plural)?

(You did not describe any mux so I can only guess, what your intention was.)

In all cases - the solution I've posted, should be a good template to
adopt it to you own requirements:

process (sel, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_1 <= in_5;
out_2 <= in_6;
out_3 <= in_7;
out_4 <= in_8;
end if;
end process;

f'up comp.lang.vhdl

Ralf

 

[valentin tihomirov]

process (SEL, I0, I1)
begin
case SEL is
when '0' => O <= I0;
when '1' => O <= I1;
when others => O <= 'X'; -- optional line
end case;
end process;

http://www.google.com/search?sourceid=navclient&ie=UTF-8&q=mux2+vhdl