Mutli-Level Logic To 2-Level Logic Conversion

Greetings,

Anybody knows of a tool/flow in Cadence to convert a multi-level
Verilog netlist (combinational, no flipflop) to a 2-level whatever
format netlist? Any tool (in Perl/C by anyone) which can do this
conversion?

Synopsys DC supports saving a design with Espresso PLA format but it
expects the original netlist to be in 2-level format too (or so does my
version 2002.05 report).

Thanks for the hint/info.

Regards,

Hrh.