multiply/divide algorithm

S

skyworld

Guest
Hi,
I was assigned a task to finish some algorithm with multiply and divide
with signed floating data in ASIC. I wonder if I can use "*" or "/"
directly in verilog and I don't know how many clocks it will cost until
I get the result. Since this task will be verified through FPGA, I
can't infer DW directly. Can any body give me the answer? thanks very
much.


regards

chen yong
 
FPGA's have built in multipliers and also you can choose the latency,
so thats not an issue but divide if not in powers of two should be
designed explicitlly by you.
 
well, the problem is that the design will be transfered to ASIC. So i
have to find some way which could be used at both situation.
 
The big question is with your synthesis. If your synthesis tool is targeted
to the ASIC and its available libraries, it's possible the multiply and
divide could be implemented with those operators. Your synthesizer should
have a reference that includes synthesis language support. It's in this
section that I find details for FPGAs but I don't know about your ASICs.


"skyworld" <chenyong20000@gmail.com> wrote in message
news:1124862365.814929.103790@g47g2000cwa.googlegroups.com...
Hi,
I was assigned a task to finish some algorithm with multiply and divide
with signed floating data in ASIC. I wonder if I can use "*" or "/"
directly in verilog and I don't know how many clocks it will cost until
I get the result. Since this task will be verified through FPGA, I
can't infer DW directly. Can any body give me the answer? thanks very
much.


regards

chen yong
Click to expand...
 
well, that is my point. I just want to find a solution that I can work
at both situation. My idea is to find a algorithm which could be
implemented by hardware with small cost.
 
"skyworld" <chenyong20000@gmail.com> wrote in message
news:1125108841.723522.287180@g44g2000cwa.googlegroups.com...
well, that is my point. I just want to find a solution that I can work
at both situation. My idea is to find a algorithm which could be
implemented by hardware with small cost.
Click to expand...
Then... what's your question again? I thought it was "can I use the '*' or
'/' operator directly?" It wasn't clear if you needed portable code between
FPGA, ASIC *and* RTL simulation.
 
well, you see, i am not sure if i can use '*' or '/' directly. so i
think it is better to find some portable code. Or i have to face
synthesis and simulation problem.



John_H 写道：

"skyworld" <chenyong20000@gmail.com> wrote in message
news:1125108841.723522.287180@g44g2000cwa.googlegroups.com...
well, that is my point. I just want to find a solution that I can work
at both situation. My idea is to find a algorithm which could be
implemented by hardware with small cost.

Then... what's your question again? I thought it was "can I use the '*' or
'/' operator directly?" It wasn't clear if you needed portable code between
FPGA, ASIC *and* RTL simulation.
Click to expand...
 
So, again, what's your question?


"skyworld" <chenyong20000@gmail.com> wrote in message
news:1125364469.583427.163770@g47g2000cwa.googlegroups.com...
well, you see, i am not sure if i can use '*' or '/' directly. so i
think it is better to find some portable code. Or i have to face
synthesis and simulation problem.



John_H ??:

"skyworld" <chenyong20000@gmail.com> wrote in message
news:1125108841.723522.287180@g44g2000cwa.googlegroups.com...
well, that is my point. I just want to find a solution that I can work
at both situation. My idea is to find a algorithm which could be
implemented by hardware with small cost.

Then... what's your question again? I thought it was "can I use the '*'
or
'/' operator directly?" It wasn't clear if you needed portable code
between
FPGA, ASIC *and* RTL simulation.
Click to expand...
 
that is: is there any algorithm which i could use to implement multiply
and divide by verilog?
 
On 30 Aug 2005 22:10:38 -0700, "skyworld" <chenyong20000@gmail.com>
wrote:

that is: is there any algorithm which i could use to implement multiply
and divide by verilog?
Click to expand...
no, i am afraid there are no algorithms which can be used to implement
multiply and divide by verilog. to get such an algorithm you should
take a class at the following university http://www.hogwarts.edu
 
sorry, i can't access this site. are you sure you give me a correct
address?
 
...there are no algorithms which can be used to implement
multiply and divide by verilog. to get such an algorithm you should
take a class at the following university http://www.hogwarts.edu

sorry, i can't access this site. are you sure you give me a correct
address?
Click to expand...
First, read more about Verilog and practise using it. With that
knowledge and a little thought before you ask a question, you'll find
you don't need to enrol on that course.

Newsgroups like this should be your last resort, when you really can't
solve a problem after you've tried hard. I'm not a Verilog expert,
but I think it's only polite to make some basic efforts before
pestering the experts who spend time reading messages here.
 
"skyworld" <chenyong20000@gmail.com> wrote in message
news:1125465038.773039.135260@g44g2000cwa.googlegroups.com...
that is: is there any algorithm which i could use to implement multiply
and divide by verilog?
Click to expand...
Bottom line: yes there are algorithms to do multiply and divide.
Where are these algorithms found? Here and there - all over but hard to
find.
Multiplies and divides are typically optimized to the target hardware where
ASICs have precompiled libraries and FPGAs have dedicated silicon to handle
fixed-point multiplies. Division takes longer than mults because it's
typically performed in a similar manner to how we do long division.
Floating point is typically a standards-related endeavor and less useful in
systems with dedicated functionality (dealing with numbers in a restricted
range) as opposed to generic needs like those in a processor.

If you want floating point multiplies and divides, you'll probably need to
find existing IP that costs money or is (at best) slightly supported in such
places as www.opencores.org. The functionality might seem basic enough that
everyone should have something in their tool box. The reality is the
optimized silicon and libraries keeps us from doing our own algorithms
unless we absolutely have to. Most hardware folks stay away from floating
point, using fixed-point representations instead.

If you want to do simulation and synthesis for both ASICs and FPGAs,
consider using code optimized for the ASIC and code optimized for the FPGA
and verify the two modules/algorithms produce the same results.

I'm sorry that responses to your post weren't all attempting to be helpful
responses. Consider asking a question that can be answered well in the
first place and you may get better responses.
 
Hi John_H,
thanks. well, in asic simulation I infer DW and when i run for FPGA, I
inferred FPGA libraries. I just feel a little trouble. Well, seems that
is the only way i can do.
 
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