multiplier,CLK-insufficient RECOVERY time after async CLEAR

[ranbow]

hello,
when i do timing simulation with multiplier(WHETHER the one generated
by the CORE generator system OR the macro created by the vhdl source
file),such error messages always appear:

Simul:10.9ns:H1/U3/product_reg<7>.CLK-insufficient RECOVERY time after
async CLEAR,missing time 1.6ns
……………………
Simul:90.9ns:H1/U3/product_reg<2>.IN-too short SETUP time,missing time
1ns
……………………

i can't see why i am getting these error messages.
Can anyone help me?

 

[Mike Treseler]

ranbow wrote:

hello,
when i do timing simulation with multiplier(WHETHER the one generated
by the CORE generator system OR the macro created by the vhdl source
file),such error messages always appear:

Simul:10.9ns:H1/U3/product_reg<7>.CLK-insufficient RECOVERY time after
async CLEAR,missing time 1.6ns
……………………
Simul:90.9ns:H1/U3/product_reg<2>.IN-too short SETUP time,missing time
1ns
……………………

i can't see why i am getting these error messages.

Sounds like you need to synchronize the reset pulse
in your testbench.

Did your design pass functional simulation
and static timing?

-- Mike Treseler

 

[ranbow]

I use foundation2.1i to do simulation.

My design has passed functional simulation.

There's only timing,i can't pass it.i don't know if it is static.

one of the input data is synchronized with the clock,the other is a constant.

how to synchronize the reset pulse in the testbench?

 

[Mike Treseler]

ranbow wrote:

I use foundation2.1i to do simulation.
Using modelsim?
My design has passed functional simulation.
Post the code.

how to synchronize the reset pulse in the testbench?

You could deassert reset on the falling edge of the clock.

-- Mike Treseler

 

[ranbow]

I deasserted reset on the falling edge of the clock and the problem
"insufficient RECOVERY time after async CLEAR,missing time 1.6ns" has
been solved.Thank you.

but another error message still appeared.The tool i use isn't
modelsim.

The following is the source code of the multiplier:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m13x10v is
port (
ai: in STD_LOGIC_VECTOR (12 downto 0);
bi: in STD_LOGIC_VECTOR (9 downto 0);
clk:in std_logic;
product: out STD_LOGIC_VECTOR (22 downto 0);
done: out STD_LOGIC
);
end m13x10v;

architecture m13x10v_arch of m13x10v is
begin
process(clk,ai,bi)
variable a,b,m:std_logic_vector(12 downto 0);
variable count:integer;
begin
if clk'event and clk='1' then
a:=ai;
b:="000"&bi;
m:="0000000000000";
done<='0';
for I in 0 to 12 loop
if a(0)='1' then
m:=m+bi;
end if;
a:=m(0)& a(12 downto 1);
m:='0'& m(12 downto 1);
end loop;
product<=m(9 downto 0)&a;
done<='1';
end if;
end process;
end m13x10v_arch;

You can check it and do simulation.

 

[Mike Treseler]

ranbow wrote:

I deasserted reset on the falling edge of the clock and the problem
"insufficient RECOVERY time after async CLEAR,missing time 1.6ns" has
been solved.Thank you.

but another error message still appeared.The tool i use isn't
modelsim.

.. . .code deleted

You can check it and do simulation.

Post your vhdl testbench, and I would be
happy to do that. The problem I see right away
is that your variables b and count are never used,
and there are no comments describing how you
expect these shifts and adds to work.

If this is an industrial application,
consider using an fpga with a built-in multiplier.

-- Mike Treseler

 

[ranbow]

Thanks a lot.I'm a beginner.
I always use Schematic Editor because sometimes the vhdl file is hard
to synthesize.

Can you tell me which one is better,the schematic-Based design or
HDL-based design?
Can you recommend the type of fpga with a built-in multiplier?And how
much it will cost?

 

[Mike Treseler]

ranbow wrote:

Can you tell me which one is better,the schematic-Based design or
HDL-based design?

I think starting with schematics is a good way
to learn fpga hardware and how to do
place and route and static timing analysis.

The downside is that simulation is
very tedious without an HDL.

Can you recommend the type of fpga with a built-in multiplier?And how
much it will cost?

http://www.google.com/search?q=fpga+dsp+block+multiply


-- Mike Treseler