Multiplexer...

[Julian]

Sorry if this question is too newbie, but I dont't know how to actually do
this. I need to have a two input multiplexer.

For a one input multiplexer I know I can do:

assign my_signal = (when_this_is_true) ? (assign_this_value) :
(if_not_true_this_is_assigned);

But in pseudo code I would like to write:
if one thing is true assign A to my_signal, or if another thing is true
assign B to my_signal else assign C to my_signal. Could I do this with the
simple assign statement?
Or do I have to write a "regular" if-statement?

P.S. The code needs to be syntheziable!

Best Regards
Julian

 

[Ajeetha Kumari]

Hi,
You can concatenate "?" operators as in:

But in pseudo code I would like to write:
if one thing is true assign A to my_signal, or if another thing is true
assign B to my_signal else assign C to my_signal. Could I do this with the
simple assign statement?

assign my_signal = (one_thing) ? (A) :
(another_thing) ? B : C;

Get hold of a book on Verilog, that should tell you much more.

HTH,
Ajeetha,
http://www.noveldv.com

"Julian" <julle@jepjep.dk> wrote in message news:<chqe6v$rbl$1@news.net.uni-c.dk>...

Sorry if this question is too newbie, but I dont't know how to actually do
this. I need to have a two input multiplexer.

For a one input multiplexer I know I can do:

assign my_signal = (when_this_is_true) ? (assign_this_value) :
(if_not_true_this_is_assigned);

Or do I have to write a "regular" if-statement?

P.S. The code needs to be syntheziable!

Best Regards
Julian

 

[John Penton]

Julian wrote:

Sorry if this question is too newbie, but I dont't know how to
actually do this. I need to have a two input multiplexer.

For a one input multiplexer I know I can do:

assign my_signal = (when_this_is_true) ? (assign_this_value) :
(if_not_true_this_is_assigned);

But in pseudo code I would like to write:
if one thing is true assign A to my_signal, or if another thing is
true assign B to my_signal else assign C to my_signal. Could I do
this with the simple assign statement?
Or do I have to write a "regular" if-statement?

If your various conditions are mutually exclusive (write something to prove
this), the following is probably the most readable:

assign output = ((condA) & inputA) |
((condB) & inputB) |
((condC) & inputC);

Or, if the conditions different values of the same signal (or group of
signals - think carefully about what "control" might be):

always @( <all input and control signals> )
case (control)
valueA : output = inputA;
valueB : output = inputB;
valueC : output = inputC;
default: output = 1'bx;
endcase

Note: "output" must be a reg.

HTH
John

--
John Penton - posting as an individual unless otherwise indicated.