Guest
Hi folks
It would appear to me that synthesis tools can now handle multiple WAIT
statements inside a single process. The case I'm interested in is that
with several
wait until rising_edge(clk);
statements.
My questions:
1. Is this allowed for synthesis?
2. This would appear to imply some sort of state-machine (actually just
a counter in this case). Would the synthesis tool use this state
machine for resource sharing? Strange question but bare with me.
Example:
process
begin
wait until rising_edge(clk);
a <= b + c;
wait until rising_edge(clk);
d <= e + f;
end process;
Would two combinatorial adders be instantiated, or just one which is
multiplexed according to the FSM/counter?
This could provide a very interesting way to explore the area vs delay
trade-off.
Thanks in advance,
Richard
It would appear to me that synthesis tools can now handle multiple WAIT
statements inside a single process. The case I'm interested in is that
with several
wait until rising_edge(clk);
statements.
My questions:
1. Is this allowed for synthesis?
2. This would appear to imply some sort of state-machine (actually just
a counter in this case). Would the synthesis tool use this state
machine for resource sharing? Strange question but bare with me.
Example:
process
begin
wait until rising_edge(clk);
a <= b + c;
wait until rising_edge(clk);
d <= e + f;
end process;
Would two combinatorial adders be instantiated, or just one which is
multiplexed according to the FSM/counter?
This could provide a very interesting way to explore the area vs delay
trade-off.
Thanks in advance,
Richard