multiple Tacc with PLI

L

laureline

Guest
Hello,

I made a verilog model for a flash memory. In this memory, the access time (Tacc) is asynchronous and conditioned by the state of input pins and triggered by ATD_TRIG rising edge. There are 4 different access times triggered by the same ATD_TRIG.

tpd_ATD_TRIG_DOUT_lh = `flash$tacc,
tpd_ATD_TRIG_DOUT_hl = `flash$tacc,
tpd_ATD_TRIG_FTRIMR_DOUT_lh = `flash$tacchs,
tpd_ATD_TRIG_FTRIMR_DOUT_hl = `flash$tacchs,
tpd_ATD_TRIG_VREAD0_DOUT_lh = `flash$taccv0,
tpd_ATD_TRIG_VREAD0_DOUT_hl = `flash$taccv0,
tpd_ATD_TRIG_VREAD1_DOUT_lh = `flash$taccv1,
tpd_ATD_TRIG_VREAD1_DOUT_hl = `flash$taccv1,
…
if (!FTRIMR[58]&!VREAD0&!VREAD1)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_DOUT[0]_lh , \tpd_ATD_TRIG_DOUT[0]_hl );
if (FTRIMR[58]&!VREAD0&!VREAD1)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_FTRIMR_DOUT[0]_lh , \tpd_ATD_TRIG_FTRIMR_DOUT[0]_hl );
if (VREAD0&!VREAD1)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_VREAD0_DOUT[0]_lh , \tpd_ATD_TRIG_VREAD0_DOUT[0]_hl );
if (VREAD1&!VREAD0)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_VREAD1_DOUT[0]_lh , \tpd_ATD_TRIG_VREAD1_DOUT[0]_hl );


During the functional SoC simulation there were no problems, we can clearly see our different Tacc, however, during back-annotation phase, when the PLI is loaded, we have an issue :
If we look in detail what the pli is doing during the compilation, it rebuilds a “matrix” for the arc of Tacc with input pins – output pins.
In my case, I have 4 timings for the same couple input-output, so it overwrites the previous value with the next one, and at the end we have only 1 timing back annotated.

-I- [PLI] Current modpath is 'tb_ascnvm1024k.ascnvm1024k_dut.ATD_TRIG_DOUT[0]'.
-I- [PLI] Current modpath root is 'ATD_TRIG_DOUT'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_lh'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_hl'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [PLI] Output pin : '0' .
-I- [PLI] Modpath_name : 'tpd_ATD_TRIG_DOUT[0]' .
-I- [PLI] Modpath_rise_name : 'tpd_ATD_TRIG_DOUT[0]_lh' .
-I- [PLI] Modpath_fall_name : 'tpd_ATD_TRIG_DOUT[0]_hl' .
-I- [PLI] Rise path internal delay : '38.000000'.
-I- [PLI] Fall path internal delay : '38.000000'.
-I- [PLI] Modpath is 'ATD_TRIG_DOUT[0]' ( [lh] 38.000000:38.000000:38.000000 [hl] 38.000000:38.000000:38.000000 ) vs ( [lh] 38.000000 [hl] 38.000000 )..

…

-I- [PLI] Current modpath is 'tb_ascnvm1024k.ascnvm1024k_dut.ATD_TRIG_DOUT[0]'.
-I- [PLI] Current modpath root is 'ATD_TRIG_DOUT'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_lh'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_hl'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [PLI] Output pin : '0' .
-I- [PLI] Modpath_name : 'tpd_ATD_TRIG_DOUT[0]' .
-I- [PLI] Modpath_rise_name : 'tpd_ATD_TRIG_DOUT[0]_lh' .
-I- [PLI] Modpath_fall_name : 'tpd_ATD_TRIG_DOUT[0]_hl' .
-I- [PLI] Rise path internal delay : '38.000000'.
-I- [PLI] Fall path internal delay : '38.000000'.
-I- [PLI] Modpath is 'ATD_TRIG_DOUT[0]' ( [lh] 29.000000:29.000000:29.000000 [hl] 29.000000:29.000000:29.000000 ) vs ( [lh] 38.000000 [hl] 38.000000 )..

Has anybody already seen this case before ? How do you modify the PLI(?) to get every arc back-annotated ?

Thanks for your help.
Laureline
 
In article <7b235378-c01a-497e-840d-6387b1f5dde5@googlegroups.com>,
laureline <laureline.bour@gmail.com> wrote:
Hello,

I made a verilog model for a flash memory. In this memory, the access time (Tacc) is asynchronous and conditioned by the state of input pins and triggered by ATD_TRIG rising edge. There are 4 different access
times triggered by the same ATD_TRIG.

tpd_ATD_TRIG_DOUT_lh = `flash$tacc,
tpd_ATD_TRIG_DOUT_hl = `flash$tacc,
tpd_ATD_TRIG_FTRIMR_DOUT_lh = `flash$tacchs,
tpd_ATD_TRIG_FTRIMR_DOUT_hl = `flash$tacchs,
tpd_ATD_TRIG_VREAD0_DOUT_lh = `flash$taccv0,
tpd_ATD_TRIG_VREAD0_DOUT_hl = `flash$taccv0,
tpd_ATD_TRIG_VREAD1_DOUT_lh = `flash$taccv1,
tpd_ATD_TRIG_VREAD1_DOUT_hl = `flash$taccv1,
…
if (!FTRIMR[58]&!VREAD0&!VREAD1)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_DOUT[0]_lh , \tpd_ATD_TRIG_DOUT[0]_hl );
if (FTRIMR[58]&!VREAD0&!VREAD1)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_FTRIMR_DOUT[0]_lh , \tpd_ATD_TRIG_FTRIMR_DOUT[0]_hl );
if (VREAD0&!VREAD1)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_VREAD0_DOUT[0]_lh , \tpd_ATD_TRIG_VREAD0_DOUT[0]_hl );
if (VREAD1&!VREAD0)
( posedge ATD_TRIG => ( DOUT[0] : 1'bx ) ) = ( \tpd_ATD_TRIG_VREAD1_DOUT[0]_lh , \tpd_ATD_TRIG_VREAD1_DOUT[0]_hl );


During the functional SoC simulation there were no problems, we can clearly see our different Tacc, however, during back-annotation phase, when the PLI is loaded, we have an issue :
If we look in detail what the pli is doing during the compilation, it rebuilds a “matrix” for the arc of Tacc with input pins – output pins.
In my case, I have 4 timings for the same couple input-output, so it overwrites the previous value with the next one, and at the end we have only 1 timing back annotated.

-I- [PLI] Current modpath is 'tb_ascnvm1024k.ascnvm1024k_dut.ATD_TRIG_DOUT[0]'.
-I- [PLI] Current modpath root is 'ATD_TRIG_DOUT'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_lh'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_hl'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [PLI] Output pin : '0' .
-I- [PLI] Modpath_name : 'tpd_ATD_TRIG_DOUT[0]' .
-I- [PLI] Modpath_rise_name : 'tpd_ATD_TRIG_DOUT[0]_lh' .
-I- [PLI] Modpath_fall_name : 'tpd_ATD_TRIG_DOUT[0]_hl' .
-I- [PLI] Rise path internal delay : '38.000000'.
-I- [PLI] Fall path internal delay : '38.000000'.
-I- [PLI] Modpath is 'ATD_TRIG_DOUT[0]' ( [lh] 38.000000:38.000000:38.000000 [hl] 38.000000:38.000000:38.000000 ) vs ( [lh] 38.000000 [hl] 38.000000 ).

…

-I- [PLI] Current modpath is 'tb_ascnvm1024k.ascnvm1024k_dut.ATD_TRIG_DOUT[0]'.
-I- [PLI] Current modpath root is 'ATD_TRIG_DOUT'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_lh'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [GET_REAL_SPECPARAM] Specparam name : 'tpd_ATD_TRIG_DOUT_hl'.
-I- [GET_REAL_SPECPARAM] Specparam value : '38.000000'.
-I- [PLI] Output pin : '0' .
-I- [PLI] Modpath_name : 'tpd_ATD_TRIG_DOUT[0]' .
-I- [PLI] Modpath_rise_name : 'tpd_ATD_TRIG_DOUT[0]_lh' .
-I- [PLI] Modpath_fall_name : 'tpd_ATD_TRIG_DOUT[0]_hl' .
-I- [PLI] Rise path internal delay : '38.000000'.
-I- [PLI] Fall path internal delay : '38.000000'.
-I- [PLI] Modpath is 'ATD_TRIG_DOUT[0]' ( [lh] 29.000000:29.000000:29.000000 [hl] 29.000000:29.000000:29.000000 ) vs ( [lh] 38.000000 [hl] 38.000000 ).

Has anybody already seen this case before ? How do you modify the PLI(?) to get every arc back-annotated ?
Click to expand...

Laureline,

I don't think you're going to get much help here. SDF annotations not done by often
anymore. PLI is probably just as rare. So your pool of people that
could help is quite small.

I'm confused why they're tied together in your setup. Normally, SDF is annotated
using standard mechanisms in the verilog language ($sdf_annotate). The PLI is NOT
normally involved with SDF annotation.

The PLI is a C (or other language) interface to the verilog internals. It's not used
much outside of vendors supplying add-on-tools to verilog.

So if you're have some kind of custom PLI that's helping with SDF annotation,
you'll need to go to whoemever wrote said PLI for help. This isn't
a generic verilog question at all.

If you ARE using $sdf_annotate, and are having problems, please clarify,
and perhaps you'll find some help.

Regards,

Mark
 
Thanks for your response.
I'm going to try to remove the PLI of our flow.
 
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