Multiple sources driving a bus + synthesis / implementation

[Henk De Denktenk]

I am trying to make a bus system where multiple sources must be able
to drive the same signal. Is this possible to implement?

Right now all the sources make their outputs 'Z' if they are not
driving the bus. Only the source that is currently addressed is
driving the line ('1' or '0').

It works in simulation, but does this work when I load it into an
FPGA? My teacher told me that this is impossible to implement, but I
don't trust him too much.

(I use the APEX EP20K-something)

Thanks in advance,

Henk de Denktenk.

 

[Jan De Ceuster]

I am trying to make a bus system where multiple sources must be able
to drive the same signal. Is this possible to implement?

Right now all the sources make their outputs 'Z' if they are not
driving the bus. Only the source that is currently addressed is
driving the line ('1' or '0').

It works in simulation, but does this work when I load it into an
FPGA? My teacher told me that this is impossible to implement, but I
don't trust him too much.

(I use the APEX EP20K-something)

Thanks in advance,

Euhm, I think it works but I'm not sure about the APEX20. Off chip it works,
lots of busses do such thing.
An other sollution is to use an OR bus. In stead of driving a 'Z' when not
driving just drive a '0' on all the lines. Gate all the outputs to an OR and
wire the output from to OR to all the inputs.

Jan

 

[Nicolas Matringe]

Jan De Ceuster a écrit:

Right now all the sources make their outputs 'Z' if they are not
driving the bus. Only the source that is currently addressed is
driving the line ('1' or '0').

It works in simulation, but does this work when I load it into an
FPGA? My teacher told me that this is impossible to implement, but I
don't trust him too much.

Euhm, I think it works but I'm not sure about the APEX20. Off chip it
works, lots of busses do such thing.

It doesn't work because FPGAs don't have internal tristate drivers. Old
Xilinx families had such internal busses but their performances were not
very good and they were dropped.

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[MikeTreseler]

Yes, synthesis will convert 'Z' drive to
muxes if the enable logic is correct.
Try it and see.

Then try the same thing with a CASE
selection and see how that works.

-- Mike Treseler

 

Hi,
I used the internal tri-state bus from Xilinx Virtex II 1000 chip.

The equations are:
A(63 downto 0) <= X1(63 downto 0) when C1 else Z_64;
A(63 downto 0) <= X2(63 downto 0) when C2 else Z_64;
A(63 downto 0) <= X3(63 downto 0) when C3 else Z_64;

It runs much faster than AND/OR equations.

But you must pay attention to 2 situations:
1. All conditions for tri-state must be mutually exclusive;
2. When bus is idle, never clock the tri-state bus into a register.
Otherwise it will cause big current due to metastate situations when
tri-state is not driven by any wires: the bus not driven is floating
and it may resides on input floating area for a register.

If you can confirm the above 2 situations are well addressed, Xilinx
internal tri-state bus is really good tools to use. I use it every time
I have a chance.

Weng

 

[Jan De Ceuster]

Right now all the sources make their outputs 'Z' if they are not
driving the bus. Only the source that is currently addressed is
driving the line ('1' or '0').

It works in simulation, but does this work when I load it into an
FPGA? My teacher told me that this is impossible to implement, but I
don't trust him too much.


Euhm, I think it works but I'm not sure about the APEX20. Off chip it
works, lots of busses do such thing.


It doesn't work because FPGAs don't have internal tristate drivers. Old
Xilinx families had such internal busses but their performances were not
very good and they were dropped.

Yes I know that FPGA's don't have internal tristates but doesn't the synthesis

tool convert the behaviour to something similar but implementable on FPGA?

 

[newman5382]

"Jan De Ceuster" <jandc@elis.ugent.be> wrote in message
news:cp1s2j$ke9$1@gaudi2.UGent.be...

I am trying to make a bus system where multiple sources must be able
to drive the same signal. Is this possible to implement?

Right now all the sources make their outputs 'Z' if they are not
driving the bus. Only the source that is currently addressed is
driving the line ('1' or '0').

It works in simulation, but does this work when I load it into an
FPGA? My teacher told me that this is impossible to implement, but I
don't trust him too much.

(I use the APEX EP20K-something)

Thanks in advance,

Euhm, I think it works but I'm not sure about the APEX20. Off chip it
works, lots of busses do such thing.
An other sollution is to use an OR bus. In stead of driving a 'Z' when not
driving just drive a '0' on all the lines. Gate all the outputs to an OR
and wire the output from to OR to all the inputs.

Jan

The other solution sounds pretty good. I think the Xilinx/IBM embedded
processor busses use that method. I've read that some ASIC designers do not
like internal tri-state busses because of potential contention race
conditions, and testability issues. Also, I don't recall the details
exactly, but RTL simulations using internal tristates can fool you, because
IIRC, I think a 'Z' can propagate through an enabled output, making it look
like it is tri-stated (but don't quote me on that because at the time of
observation, I was suffering from a lack of sleep ).

- Newman