Multiple source problem...in VHDL

[samz]

I am doing a serial-parallel convertor in VHDL...
i have to output multiple output lines(four, 8bit o/ps from dff)to a
single 8bit output line.In idle state the o/p lines will be in
tristate(Z).
I am getting multiple source problem ,How can i overcome this problem?

 

[Mike Treseler]

samz wrote:

I am doing a serial-parallel convertor in VHDL...
i have to output multiple output lines(four, 8bit o/ps from dff)to a
single 8bit output line.In idle state the o/p lines will be in
tristate(Z).

Consider using separate in and out pins if you can.

I am getting multiple source problem ,How can i overcome this problem?

Consider using a single clocked process.


-- Mike Treseler

 

[Kenny]

hit the nail on the head