Multiple simulations with different parameters

[Girish]

Hi all,

I am a bit inexperienced with Verilog so please pardon me if my
question is trivial. But I would really appreciate your help since I
need this very desperately to be sorted out.
Here is my problem.

Suppose I have a full adder with carry delay as a parameter. In my
testbench, I instantiate the full adder with a particular delay and
run some testvectors, get the output. Then I want to be able to change
the carry delay to some other number and run the same inputs through it
again.
I want to do this change many (30) times so I want this to be
automatically done.

Can someone please tell me how to do this automatically ? Your help is
very much appreciated.

Thank you
Girish

 

Suppose I have a full adder with carry delay as a parameter. In my
testbench, I instantiate the full adder with a particular delay and
run some testvectors, get the output. Then I want to be able to change
the carry delay to some other number and run the same inputs through it
again.
I want to do this change many (30) times so I want this to be
automatically done.

Can someone please tell me how to do this automatically ? Your help is
very much appreciated.

Supposing that you have used the Verilog keyword "parameter" to
parameterize your design, one way to do it, is, to write a Perl script
or any other scripting language, that calls simulation executable with
different parameters.

You cannot do that within simulation, because Verilog "parameter" is
determined during the compilation/elaboration time.

That means, you assign a value to a parameter, compile the codes, run
the simulation, change the parameter and run another simulation and so
on.

Tell us which simulator you are using. If you are using NC-Sim, you can
change the parameter in ncelab, elaborator, with +defparam option. You
can call ncelab from a Perl script.

If you are using Modelsim, I think you can do that with Modelsim's own
TCL script.

The words elaboration/compilation are used in this post interchangably.

Utku.

 

[Girish]

Hi Utku,

Thank you very much for your reply.
I am using Cadence NCverilog for simulation. The steps for my
simulation are
ncvlog -work worklib -cdslib ./cds.lib -logfile ncvlog.log testfa.v
ncelab -work worklib -cdslib ./cds.lib -logfile ncelab.log
worklib.stimulus:module
ncsim -work worklib -cdslib ./cds.lib -logfile ncsim.log
worklib.stimulus:module

Supposing that you have used the Verilog keyword "parameter" to
parameterize your design, one way to do it, is, to write a Perl script
or any other scripting language, that calls simulation executable with
different parameters.

Can you please explain how to pass a parameter when you call the
simulation executable in the above lines (ncsim ... )

You cannot do that within simulation, because Verilog "parameter" is
determined during the compilation/elaboration time.
That means, you assign a value to a parameter, compile the codes, run
the simulation, change the parameter and run another simulation and so
on.

Does that mean I have to change parameter somehow, then again follow
the 3 steps.
ncvlog..., ncelab ..., ncsim ?

Tell us which simulator you are using. If you are using NC-Sim, you can
change the parameter in ncelab, elaborator, with +defparam option. You
can call ncelab from a Perl script.

Wow, it seems to be that means I can insert +defparam in the command.

ncelab -work worklib -cdslib ./cds.lib -logfile ncelab.log +defparam
delay=160 worklib.stimulus:module

Am I correct ? Please let me know
Thank you very much

Suppose I have a full adder with carry delay as a parameter. In my
testbench, I instantiate the full adder with a particular delay and
run some testvectors, get the output. Then I want to be able to change
the carry delay to some other number and run the same inputs through it
again.
I want to do this change many (30) times so I want this to be
automatically done.

Can someone please tell me how to do this automatically ? Your help is
very much appreciated.

Supposing that you have used the Verilog keyword "parameter" to
parameterize your design, one way to do it, is, to write a Perl script
or any other scripting language, that calls simulation executable with
different parameters.

You cannot do that within simulation, because Verilog "parameter" is
determined during the compilation/elaboration time.

That means, you assign a value to a parameter, compile the codes, run
the simulation, change the parameter and run another simulation and so
on.

Tell us which simulator you are using. If you are using NC-Sim, you can
change the parameter in ncelab, elaborator, with +defparam option. You
can call ncelab from a Perl script.

If you are using Modelsim, I think you can do that with Modelsim's own
TCL script.

The words elaboration/compilation are used in this post interchangably.

Utku.

 

Girish wrote:

Suppose I have a full adder with carry delay as a parameter. In my
testbench, I instantiate the full adder with a particular delay and
run some testvectors, get the output. Then I want to be able to change
the carry delay to some other number and run the same inputs through it
again.

If you have to use a parameter, then re-elaborating is required, as
someone else described. This would be true if you need to be able to
instantiate an existing full adder with different parameter values, and
you cannot modify the adder.

If you can modify the adder, you could change it to use a variable for
the delay. Then you could add an initial block using $value$plusargs
to set the value of the variable based on a command line argument to
the simulator (or you could set the value interactively). This would
avoid the need to re-elaborate the design. However, this is not the
sort of thing you could synthesize.

 

Can you please explain how to pass a parameter when you call the
simulation executable in the above lines (ncsim ... )

I am not at work now, otherwise I would have given you an example.
Overriding parameter should be done during elaboration time, ie.
"ncelab" must have "+defparam" option or something. Look at the manual.

You can change (in technical terms "override") parameter of a Verilog
design during elaboration time (ie. by calling ncelab), as someone as
described.

Does that mean I have to change parameter somehow, then again follow
the 3 steps.
ncvlog..., ncelab ..., ncsim ?

Almost. ncvlog is not required. A simple Perl script could be:

for ($i = 4; $i < 32; $i++) {
system ("ncelab +defparam+tb.delay=$i worklib.stimulus:module");
system ("ncsim worklib.stimulus:module");
}

It should be something like that. Your Perl script must have following
"algorithm":

- compile that codes first
- foreach value of $delay {
- elaborate design
- simulate design
}

Wow, it seems to be that means I can insert +defparam in the command.

Yes, you must have the version of NC-Sim that supports that.

ncelab -work worklib -cdslib ./cds.lib -logfile ncelab.log +defparam
delay=160 worklib.stimulus:module

Am I correct ? Please let me know
Thank you very much

Almost yes. Look at the example I have given above and the manual, too.
Let us know if you have problem.

Utku.

 

[Girish]

Hi Utku,

This is your suggestion. Thanks a lot for the help. I have one doubt
though.

- compile that codes first
- foreach value of $delay {
- elaborate design
- simulate design
}
for ($i = 4; $i < 32; $i++) {
system ("ncelab +defparam+tb.delay=$i worklib.stimulus:module");
system ("ncsim worklib.stimulus:module");
}

Doubt : When I say "ncsim", a new window pops up in which I need to hit
the "run" button to be able to start the simulation. Is there an
automated way to "run" the simulation rather than having to manually
hit the run button ? Please let me know if you know how to do this.
thanks
Girish




utku.ozcan@gmail.com wrote:

Can you please explain how to pass a parameter when you call the
simulation executable in the above lines (ncsim ... )

I am not at work now, otherwise I would have given you an example.
Overriding parameter should be done during elaboration time, ie.
"ncelab" must have "+defparam" option or something. Look at the manual.

You can change (in technical terms "override") parameter of a Verilog
design during elaboration time (ie. by calling ncelab), as someone as
described.

Does that mean I have to change parameter somehow, then again follow
the 3 steps.
ncvlog..., ncelab ..., ncsim ?

Almost. ncvlog is not required. A simple Perl script could be:

for ($i = 4; $i < 32; $i++) {
system ("ncelab +defparam+tb.delay=$i worklib.stimulus:module");
system ("ncsim worklib.stimulus:module");
}

It should be something like that. Your Perl script must have following
"algorithm":

- compile that codes first
- foreach value of $delay {
- elaborate design
- simulate design
}

Wow, it seems to be that means I can insert +defparam in the command.

Yes, you must have the version of NC-Sim that supports that.

ncelab -work worklib -cdslib ./cds.lib -logfile ncelab.log +defparam
delay=160 worklib.stimulus:module

Am I correct ? Please let me know
Thank you very much

Almost yes. Look at the example I have given above and the manual, too.
Let us know if you have problem.

Utku.

 

This is your suggestion. Thanks a lot for the help. I have one doubt
though.
- compile that codes first
- foreach value of $delay {
- elaborate design
- simulate design
}
for ($i = 4; $i < 32; $i++) {
system ("ncelab +defparam+tb.delay=$i worklib.stimulus:module");

I did a typo here. It must be "ncelab -defparam tb.delay=5 ..."
You must use scoping rules to override parameter, ie. the hierarchical
scope before the parameter name. In the example above I have assumed
that the parameter is defined in the testbench, and this testbench is
called "tb".

system ("ncsim worklib.stimulus:module");
}



Doubt : When I say "ncsim", a new window pops up in which I need to hit
the "run" button to be able to start the simulation. Is there an
automated way to "run" the simulation rather than having to manually
hit the run button ? Please let me know if you know how to do this.
thanks
Girish

That means that you run ncsim in GUI mode, ie. you call it "ncsim -gui
....."
If you give -gui option and if you want to start the sim automatically,
you have to pass an additional TCL script to start sim:

"ncsim -input ncsim.tcl -gui ..."

In this example above, ncsim takes a TCL script called "ncsim.tcl" and
runs it. Now, if you put following commands in this ncsim.tcl text
file:

run
exit

.... then your Perl script will call NC-Sim in GUI mode and your GUI
will start the simulation immediately, due to the script. "exit" is
crucial, to be safe. Otherwise the sim can run forever, due to a
testbench/design mistake.

But there is no mechanism thru this NC-Sim TCL script to close the GUI
after simulation ends. I therefore strongly advise you to run NC-Sim in
non-GUI mode, when you want to call NC-Sim executables from a Perl
script. It is then very easy to parameterize your project.

HTH.
Utku.

 

[Mark McDougall]

utku.ozcan@gmail.com wrote:

You cannot do that within simulation, because Verilog "parameter" is
determined during the compilation/elaboration time.
That means, you assign a value to a parameter, compile the codes, run
the simulation, change the parameter and run another simulation and so
on.

Perhaps one solution is to instantiate [30] copies of the adder, and do
the lot in a single simulation run???

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

Mark, I have other solution(s)!

Buying 30 floating licences for a simulator (or different simulators)
and running each on a separate workstation/compute machine. Massive
parallelism, saves time but the manager would kill you

Utku..

Mark McDougall wrote:

utku.ozcan@gmail.com wrote:

You cannot do that within simulation, because Verilog "parameter" is
determined during the compilation/elaboration time.
That means, you assign a value to a parameter, compile the codes, run
the simulation, change the parameter and run another simulation and so
on.

Perhaps one solution is to instantiate [30] copies of the adder, and do
the lot in a single simulation run???

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

Mark McDougall wrote:

Perhaps one solution is to instantiate [30] copies of the adder, and do
the lot in a single simulation run???

This sounds like a good idea. If the delay values are a simple function
of N (e.g. evenly spaced values), then a generate-for could instantiate
and parameterize them all very concisely.

Depending on the form of output desired, there could be some effort
required to separate out the results for each instance.

 

[Muks]

sharp@cadence.com wrote:

Mark McDougall wrote:

Perhaps one solution is to instantiate [30] copies of the adder, and do
the lot in a single simulation run???

This sounds like a good idea. If the delay values are a simple function
of N (e.g. evenly spaced values), then a generate-for could instantiate
and parameterize them all very concisely.

Here is the sample code using verilog-2k generate with for loop. This
might help you verifying your design to be tested with different delay
values based on parameter.


============ test.v ==============
module test(input [31:0] b, output reg [31:0] a);
parameter p = 1;
initial #p a = b;

endmodule

module top;
genvar i;
reg [31:0] a [1:10];
reg [31:0] b [1:10];

generate
for (i=1; i<=10; i=i+1) begin : A
test #(i) u (b,a);
end
endgenerate

initial begin
b[1] = 11;
b[2] = 10;
b[3] = 9;
b[4] = 8;
b[5] = 7;
b[6] = 6;
b[7] = 5;
b[8] = 4;
b[9] = 3;
b[10] = 2;
end

initial $monitor($time,"unit %0d, %0d, %0d, %0d, %0d, %0d, %0d, %0d,
%0d, %0d",a[1],a[2],a[3],a[4],a[5],a[6],a[7],a[8],a[9],a[10]);
endmodule

============ X =================

Simulation result:
==================
0unit x, x, x, x, x, x, x, x, x, x
1unit 11, x, x, x, x, x, x, x, x, x
2unit 11, 10, x, x, x, x, x, x, x, x
3unit 11, 10, 9, x, x, x, x, x, x, x
4unit 11, 10, 9, 8, x, x, x, x, x, x
5unit 11, 10, 9, 8, 7, x, x, x, x, x
6unit 11, 10, 9, 8, 7, 6, x, x, x, x
7unit 11, 10, 9, 8, 7, 6, 5, x, x, x
8unit 11, 10, 9, 8, 7, 6, 5, 4, x, x
9unit 11, 10, 9, 8, 7, 6, 5, 4, 3, x
10unit 11, 10, 9, 8, 7, 6, 5, 4, 3, 2
===================


Regards
Mukesh